公开(公告)号：US20180331105A1

公开(公告)日：2018-11-15

申请号：US16028080

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KOOK-TAE KIM ,  HO-SUNG SON ,  DONG-SUK SHIN ,  HYUN-JUN SIM ,  JU-RI LEE ,  SUNG-UK JANG

IPC: H01L27/092 ,  H01L29/167 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66545

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.

公开(公告)号：US20170133379A1

公开(公告)日：2017-05-11

申请号：US15276274

申请日：2016-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KOOK-TAE KIM ,  HO-SUNG SON ,  DONG-SUK SHIN ,  HYUN-JUN SIM ,  JU-RI LEE ,  SUNG-UK JANG

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/167 ,  H01L29/7851

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.