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公开(公告)号：US09098381B2
公开(公告)日：2015-08-04
申请号：US13734520
申请日：2013-01-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyoungmoon Ahn , Jonghoon Shin , Yong Ki Lee , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.
Abstract translation: 模块运算单元包括接收第一数据以产生第一操作数的第一输入发生器; 接收第二数据以产生第二操作数的第二输入发生器; 累加器执行累加/移位操作以添加第一和第二操作数并输出进位和和; 一个进位传播加法器，加上进位和和输出一个结果; 以及接收外部数据或结果并输出第一数据和第二数据的数据处理器。
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公开(公告)号：US12192319B2
公开(公告)日：2025-01-07
申请号：US17467546
申请日：2021-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyosun Hwang , Gisoo Seo , Jonghoon Shin , Hyojoon Jin , Ingoo Heo , Jinsu Hyun
IPC: G06F21/72 , G06F7/58 , G06F17/11 , G06F21/55 , G06F21/75 , G06F21/78 , H04L9/00 , H04L9/08 , G06F7/72
Abstract: A device includes a random number generator configured to generate a random number, a memory configured to store at least one lookup table, and a processing circuit configured to generate a generator based on the random number, create the at least one lookup table based on the generator, and write the created at least one lookup table to the memory, wherein the processing circuit is configured to access the memory based on a first input and a second input, and generate a result of a modular multiplication of the first input by the second input based on the at least one lookup table.
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公开(公告)号：US09448768B2
公开(公告)日：2016-09-20
申请号：US13792642
申请日：2013-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
Abstract translation: 提供了一种模数乘法器和一种模乘法。 模数乘法器包括：第一寄存器，其存储在先前周期计算的先前累积值; 存储在前一周期计算的先前商的第二寄存器; 商产生器，其使用从所述第一寄存器输出的存储的先前累积值生成商; 以及累加器，其接收操作数，乘数的位值，存储的先前累积值和存储的先前商，以计算当前周期中的累积值，其中计算的累加值被更新为第一寄存器，并且 生成商被更新到第二个寄存器。
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4.发明授权公开(公告)号：US09164732B2
公开(公告)日：2015-10-20
申请号：US14139113
申请日：2013-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Sun-Soo Shin , Jonghoon Shin , Kyoung Moon Ahn , Ji-Su Kang , Kee Moon Chun
CPC classification number: G06F7/722 , G06F7/728 , H04L9/3013 , H04L9/302
Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.
Abstract translation: 提供乘法和模乘法。 乘法方法包括：通过向乘法器添加重新编码常数来变换冗余形式乘法器，通过使用变换乘数执行重新编码，并且使用重新编码的结果值，在乘法器和乘法器之间执行部分乘法。
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公开(公告)号：US11593527B2
公开(公告)日：2023-02-28
申请号：US17060099
申请日：2020-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehyeok Kim , Hyesoo Lee , Hongmook Choi , Jisu Kang , Hyunil Kim , Jonghoon Shin
Abstract: A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.
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Patent Agency Ranking
公开(公告)号：US11070380B2
公开(公告)日：2021-07-20
申请号：US15212343
申请日：2016-07-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kitak Kim , Ji-Su Kang , Kiseok Bae , Jonghoon Shin , Kyoungmoon Ahn , Jinsu Hyun
Abstract: An authentication apparatus, included in a device supporting a network communication, includes a certificate handler that receives a certificate of an opponent and parses or verifies the certificate of the opponent. Cryptographic primitives receive an authentication request of the opponent, generate a random number in response to the authentication request, generate a challenge corresponding to the random number, and verify a response of the opponent corresponding to the challenge. A shared memory stores the parsed certificate, the random number, the challenge, and the response. An authentication controller controls the certificate handler, the cryptographic primitives, and the shared memory through a register setting, according to an authentication protocol.
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公开(公告)号：US09841950B2
公开(公告)日：2017-12-12
申请号：US15242768
申请日：2016-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
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公开(公告)号：US09811318B2
公开(公告)日：2017-11-07
申请号：US14672656
申请日：2015-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jonghoon Shin , Sun-Soo Shin , Kyoungmoon Ahn , Yong Ki Lee
CPC classification number: G06F7/728 , G06F7/5338
Abstract: A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.
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公开(公告)号：US20210264061A1
公开(公告)日：2021-08-26
申请号：US17060099
申请日：2020-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehyeok Kim , Hyesoo Lee , Hongmook Choi , Jisu Kang , Hyunil Kim , Jonghoon Shin
Abstract: A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.
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公开(公告)号：US10897687B2
公开(公告)日：2021-01-19
申请号：US16566058
申请日：2019-09-10
Applicant: Samsung Electronics Co., Ltd. , INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Inventor： Taejun Kwon , Seongil Hahm , Jonghoon Shin , Kyoungwoo Lee , Hyunchoong Kim
Abstract: An electronic device and a method for identifying a location by the electronic device are provided. The electronic device includes a display, a processor electrically connected with the display and a memory, and the memory storing instructions executed by the processor. The processor is configured to obtain a plurality of locations in a space-of-interest, detect a wireless signal from at least one external electronic device located in the space-of-interest or an adjacent area, obtain detection frequency data according to a frequency of detection of the wireless signal, and identify a current location of the electronic device based on at least part of the obtained detection frequency data.
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