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    Methods of thermally treating a semiconductor wafer
    2.
    发明授权
    Methods of thermally treating a semiconductor wafer 有权
    热处理半导体晶片的方法

    公开(公告)号：US08854614B2

    公开(公告)日：2014-10-07

    申请号：US13715099

    申请日：2012-12-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Hoon Kang ,  Taegon Kim ,  Hanmei Choi ,  Eunyoung Jo ,  Gonsu Kang ,  Sungho Kang ,  Sungho Heo

    IPC: G01N21/00 ,  H01L21/66 ,  H01L21/68 ,  H01L21/324 ,  H01L21/67

    CPC classification number: H01L21/324 ,  H01L21/67115 ,  H01L21/67288 ,  H01L21/681 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20

    Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

    Abstract translation: 一种热处理晶片的方法包括将晶片装载到具有一个或多个均匀温度梯度区域和一个或多个不均匀温度梯度区域的处理室中。 在晶片中检测到缺陷。 将晶片对准以将缺陷定位在均匀温度梯度的一个或多个区域之一内。 在处理室中的晶片上执行快速热处理，同时将缺陷定位在均匀温度梯度的一个或多个区域之一内。

    Method of manufacturing semiconductor device having doped layer
    3.
    发明授权
    Method of manufacturing semiconductor device having doped layer 有权
    制造具有掺杂层的半导体器件的方法

    公开(公告)号：US09236259B2

    公开(公告)日：2016-01-12

    申请号：US14276213

    申请日：2014-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun-Young Jo ,  Jong-Hoon Kang ,  Tae-Gon Kim ,  Han-Mei Choi

    IPC: H01L21/28 ,  H01L21/225 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L21/28035 ,  H01L21/2255 ,  H01L21/28061 ,  H01L21/823842 ,  H01L29/66575

    Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.

    Abstract translation: 可以提供制造具有掺杂层的半导体器件的方法。 该方法包括提供具有第一区域和第二区域的衬底，在衬底上形成栅极电介质层，在栅极电介质层上形成第一栅电极层，在第一栅电极层上形成第一掺杂层，形成第 在所述第一掺杂层上形成第一覆盖层，在所述第一区域中的所述第一覆盖层上形成掩模图案，所述掩模图案在所述第二区域中暴露所述第一覆盖层，在所述第二区域中去除所述第一覆盖层和所述第一掺杂层 去除所述掩模图案，以及在所述第一区域中的所述第一覆盖层和所述第二区域中的所述第一栅极电极层上形成第二掺杂层。

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