公开(公告)号：US20210073166A1

公开(公告)日：2021-03-11

申请号：US16952681

申请日：2020-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-yeon JEON ,  Jae-Gon LEE ,  Youn-Sik CHOI ,  Min-joung LEE ,  Jin-ook SONG

IPC: G06F13/42 ,  G06F13/364

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

公开(公告)号：US20250036292A1

公开(公告)日：2025-01-30

申请号：US18919119

申请日：2024-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghan LEE ,  Seongsik HWANG ,  Chon Yong LEE ,  Jae-Gon LEE

IPC: G06F3/06 ,  G06F12/1009

Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.

公开(公告)号：US20190235788A1

公开(公告)日：2019-08-01

申请号：US15949934

申请日：2018-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Jae-Gon LEE ,  Indong KIM

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679

Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.

公开(公告)号：US20230350832A1

公开(公告)日：2023-11-02

申请号：US18132734

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghan LEE ,  Jae-Gon LEE ,  Chon Yong LEE

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/1668 ,  G06F13/4081

Abstract: A storage device includes a nonvolatile memory device that stores user data, and a storage controller that controls the nonvolatile memory device under control of a host device. The storage controller includes a storage interface circuit that communicates with the host device through a compute express link (CXL) interface, a NAND interface circuit that communicates with the nonvolatile memory device, and a processor that loads map data from an external memory device through the storage interface circuit and controls the nonvolatile memory device through the NAND interface circuit based on the map data.

公开(公告)号：US20250068355A1

公开(公告)日：2025-02-27

申请号：US18947682

申请日：2024-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chon Yong LEE ,  Jae-Gon LEE ,  Kyung-Chang RYOO ,  Kyunghan LEE ,  Hyeyoung RYU

IPC: G06F3/06

Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.

公开(公告)号：US20230376216A1

公开(公告)日：2023-11-23

申请号：US18131646

申请日：2023-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghan LEE ,  Seongsik HWANG ,  Chon Yong LEE ,  Jae-Gon LEE

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0619 ,  G06F12/1009 ,  G06F3/0656 ,  G06F3/0679

Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.

公开(公告)号：US20200052405A1

公开(公告)日：2020-02-13

申请号：US16608621

申请日：2018-04-19

Applicant: Samsung Electronics Co., Ltd. ,  Hongik University Industry-Academia Cooperation Foundation

Inventor： Jae-Seok PARK ,  Jeong-Hae LEE ,  Jae-Hyun PARK ,  Kwi-Seob UM ,  Young-Ho RYU ,  Chang-Hyun LEE ,  Sang-Wook KWON ,  Sung-Bum PARK ,  Jae-Gon LEE ,  Sang-Wook CHI

IPC: H01Q9/04 ,  H01Q1/48 ,  H01Q1/24 ,  H01Q3/36 ,  H01Q15/14

Abstract: In various embodiments, a metamaterial structure antenna may comprise: a feed line for feeding a signal; a ground plane comprising a cross-shaped aperture forming circular polarization on the basis of a magnetic field induced by the fed signal; and a patch plane formed parallel to the ground plane which emits electromagnetic waves on the basis of the circular polarization.

公开(公告)号：US20190339732A1

公开(公告)日：2019-11-07

申请号：US16512849

申请日：2019-07-16

Applicant: Samsung Electronics CO., Ltd.

Inventor： Youn-Sik CHOI ,  Jin-Ook SONG ,  Ho-Yeon JEON ,  Jae-Gon LEE

IPC: G06F1/06 ,  G06F1/04 ,  H04J3/06 ,  H04L7/00

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

公开(公告)号：US20190236030A1

公开(公告)日：2019-08-01

申请号：US16103058

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young LIM ,  Dimin NIU ,  Jae-Gon LEE

IPC: G06F12/14 ,  G06F3/06 ,  G06F21/79

CPC classification number: G06F12/1433 ,  G06F3/0622 ,  G06F3/0679 ,  G06F21/79

Abstract: A memory module includes a random access memory (RAM) device that includes a first storage region and a second storage region, a nonvolatile memory device, and a controller that controls the RAM device or the nonvolatile memory device under control of a host. The controller includes a data buffer that temporarily stores first data received from the host, and a buffer returning unit that transmits first release information to the host when the first data are moved from the data buffer to the first storage region or the second storage region of the RAM device and transmits second release information to the host when the first data are moved from the second storage region to the nonvolatile memory device.

公开(公告)号：US20170102730A1

公开(公告)日：2017-04-13

申请号：US15388366

申请日：2016-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Sik CHOI ,  Jin-Ook SONG ,  Ho-Yeon JEON ,  Jae-Gon LEE

IPC: G06F1/06 ,  H04L7/00 ,  H04J3/06

CPC classification number: G06F1/06 ,  G06F1/04 ,  H04J3/0685 ,  H04L7/0008

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.