公开(公告)号：US20220374033A1

公开(公告)日：2022-11-24

申请号：US17591707

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yeon JEON ,  Mun Won LEE

IPC: G05F1/46 ,  G05F1/565 ,  H02M3/158

Abstract: A system-on-chip is provided. The SoC includes a system power supply circuit which outputs a first supply voltage, an intellectual property (IP) which receives the first supply voltage and operates at a second supply voltage, a supplemental power supply circuit which generates a supplemental voltage; and a comparator which compares the first supply voltage with the second supply voltage and outputs a comparison signal, wherein the supplemental voltage is provided to the IP based on the comparison signal.

公开(公告)号：US20190339732A1

公开(公告)日：2019-11-07

申请号：US16512849

申请日：2019-07-16

Applicant: Samsung Electronics CO., Ltd.

Inventor： Youn-Sik CHOI ,  Jin-Ook SONG ,  Ho-Yeon JEON ,  Jae-Gon LEE

IPC: G06F1/06 ,  G06F1/04 ,  H04J3/06 ,  H04L7/00

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

公开(公告)号：US20170102730A1

公开(公告)日：2017-04-13

申请号：US15388366

申请日：2016-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Sik CHOI ,  Jin-Ook SONG ,  Ho-Yeon JEON ,  Jae-Gon LEE

IPC: G06F1/06 ,  H04L7/00 ,  H04J3/06

CPC classification number: G06F1/06 ,  G06F1/04 ,  H04J3/0685 ,  H04L7/0008

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

公开(公告)号：US20190057733A1

公开(公告)日：2019-02-21

申请号：US15946992

申请日：2018-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Yeon JEON ,  Ah Chan KIM ,  Min Joung LEE ,  Youn-Sik CHOI

IPC: G11C11/34 ,  G06F11/34 ,  G06F13/28 ,  H03M9/00

Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.