公开(公告)号：US20210043244A1

公开(公告)日：2021-02-11

申请号：US16810527

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGHYUK CHOI ,  BONGSOON LIM ,  JAEDUK YU

IPC: G11C11/408 ,  G11C11/4094 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C5/02

Abstract: A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.

公开(公告)号：US20230307353A1

公开(公告)日：2023-09-28

申请号：US17933770

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOHAN LEE ,  CHAEHOON KIM ,  JAEDUK YU ,  JIHO CHO

IPC: H01L23/522 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L27/11582

Abstract: A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.