公开(公告)号：US20230232606A1

公开(公告)日：2023-07-20

申请号：US17950185

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Younglim Park

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L28/75

Abstract: A semiconductor device of the disclosure includes a substrate, a capacitor contact structure electrically connected to the substrate, a lower electrode connected to the capacitor contact structure, a capacitor insulating layer covering the lower electrode, and an upper electrode covering the capacitor insulating layer. The upper electrode includes a multiple layer on the capacitor insulating layer, and a cover layer on the multiple layer. The multiple layer includes a first electrode layer, a second electrode layer, and a first metal silicide layer between the first and second electrode layers. A work function of the first metal silicide layer is greater than a work function of the first electrode layer and a work function of the second electrode layer.

公开(公告)号：US20240292596A1

公开(公告)日：2024-08-29

申请号：US18489189

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Jungmin Park ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033

Abstract: A semiconductor device includes a lower structure, a capacitor on the lower structure, the capacitor including a first bottom electrode, which is extended in a direction perpendicular to a bottom surface of the lower structure, and a second bottom electrode, which is provided on the first bottom electrode, a bottom supporting pattern supporting the first bottom electrode, and a top supporting pattern provided on the bottom supporting pattern to support the first bottom electrode. The first bottom electrode includes a first material, and the second bottom electrode may include a second material. A work function of the second material is greater than a work function of the first material.

公开(公告)号：US20230225112A1

公开(公告)日：2023-07-13

申请号：US17949356

申请日：2022-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglim Park ,  Jimin Chae ,  Chanhoon Park ,  Dongmin Shin ,  Jaesoon Lim ,  Intak Jeon

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

Abstract: A semiconductor device including a substrate, lower electrodes disposed on the substrate, at least one support layer in contact with the lower electrodes, a dielectric layer disposed on the lower electrodes, an upper electrode disposed on the dielectric layer, a first interfacial film between the lower electrodes and the dielectric layer, and a second interfacial film between the upper electrode and the dielectric layer. At least one of the first and second interfacial films includes a plurality of layers, wherein the plurality of layers include a first metal element, and a second metal element, and at least one of oxygen \and nitrogen. The lower electrodes include the first metal element. A first region of the first interfacial film includes the second metal element at a first concentration and a second region of the first interfacial film includes the second metal element at a second concentration different from the first concentration.

公开(公告)号：US20240105765A1

公开(公告)日：2024-03-28

申请号：US18461408

申请日：2023-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Park ,  Intak Jeon ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H01G4/30 ,  H10B12/00

CPC classification number: H01L28/92 ,  H10B12/0335 ,  H10B12/315

Abstract: A capacitor structure includes a first lower conductive pattern, a first capacitor, a first upper conductive pattern, a second lower conductive pattern, a second capacitor and a second upper conductive pattern. The first capacitor includes first lower electrodes, first upper electrodes and first dielectric structures. Each of the first dielectric structures are disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes. The first upper conductive pattern is formed on and is electrically connected to the first upper electrodes. The second lower conductive pattern is spaced apart from the first lower conductive pattern disposed on the substrate. The second capacitor includes second lower electrodes, second upper electrodes and second dielectric structures. The second upper conductive pattern is formed on and is electrically connected to the second upper electrodes. The first and second conductive patterns are electrically insulated from each other.

公开(公告)号：US20240030024A1

公开(公告)日：2024-01-25

申请号：US18137339

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/31055

Abstract: In a method of a method of depositing a layer, a substrate is loaded on a substrate stage within a chamber. A precursor gas and a reaction gas are alternately supplied into the chamber to form at least one atomic layer. A surface of the at least one atomic layer is planarized by applying pressure on the surface of the at least one atomic layer to diffuse atoms located on the surface having a relatively high curvature. The precursor gas and the reaction gas are alternately supplied into the chamber to form at least one atomic layer on the planarized atomic layer.

公开(公告)号：US12199138B2

公开(公告)日：2025-01-14

申请号：US17941688

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Jiye Baek ,  Hanjin Lim

IPC: H10B12/00 ,  H01L49/02

Abstract: A semiconductor device of the disclosure may include a substrate, a gate structure on the substrate, a capacitor contact structure connected to the substrate, a lower electrode connected to the capacitor contact structure, a supporter supporting a sidewall of the lower electrode, an interfacial layer covering the lower electrode and including a halogen material, a capacitor insulating layer covering the interfacial layer and the supporter, and an upper electrode covering the capacitor insulating layer. The interfacial layer may include a first surface contacting the lower electrode, and a second surface contacting the capacitor insulating layer. The halogen material of the interfacial layer may be closer to the first surface than to the second surface.

公开(公告)号：US20230363142A1

公开(公告)日：2023-11-09

申请号：US18130769

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H10B12/00

CPC classification number: H10B12/31 ,  H10B12/033

Abstract: A semiconductor memory device includes an interlayer insulating layer, a plurality of first contact pads embedded in the interlayer insulating layer, a plurality of first work function adjustment patterns embedded in the interlayer insulating layer and disposed on the plurality of first contact pads, and a plurality of lower electrodes disposed on the plurality of first work function adjustment patterns.

公开(公告)号：US20230117391A1

公开(公告)日：2023-04-20

申请号：US17844623

申请日：2022-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Hyukwoo Kwon ,  Hanjin Lim

IPC: H01L27/108

Abstract: An integrated circuit semiconductor device includes a lower electrode formed on a substrate extending in a first direction and a second direction perpendicular to the first direction and a support structure supporting the lower electrode. The support structure includes a support pattern surrounding the lower electrode, extending in the first direction and the second direction, and having a hole through which the lower electrode passes, and a concavo-convex structure having at a surface of the support pattern a plurality of convex portions extending in a third direction perpendicular to the first direction and the second direction, and a plurality of concave portions arranged between the convex portions.