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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230047345A1

    公开(公告)日：2023-02-16

    申请号：US17680617

    申请日：2022-02-25

    Applicant: SAMSUNG ELECTRONICS CO.,LTD.

    Inventor： Inhyo HWANG ,  Young Lyong Kim

    IPC: H01L25/065 ,  H01L23/498

    Abstract: Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240395719A1

    公开(公告)日：2024-11-28

    申请号：US18390834

    申请日：2023-12-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo CHUNG ,  Joonghyun BAEK ,  Inhyo HWANG

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

    Abstract: Provided is a semiconductor package including a redistribution substrate, a bridge chip on the redistribution substrate, a first conductive post and a second conductive post on the redistribution substrate and spaced apart from the bridge chip, a first semiconductor chip on the bridge chip and the first conductive post, a second semiconductor chip on the bridge chip and the second conductive post, and a first mold layer on the redistribution substrate, the bridge chip, the first semiconductor chip, and the second semiconductor chip, wherein the bridge chip includes a bridge die connected to an active surface of the first semiconductor chip and an active surface of the second semiconductor chip, a second mold layer on the bridge die, a penetration via adjacent to the bridge die and vertically penetrating the second mold layer, and a capacitor disposed a bottom surface of the second mold layer and connected to the penetration via.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220208743A1

    公开(公告)日：2022-06-30

    申请号：US17696157

    申请日：2022-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ae-Nee JANG ,  Inhyo HWANG

    IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230069511A1

    公开(公告)日：2023-03-02

    申请号：US17834066

    申请日：2022-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Inhyo HWANG

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210233897A1

    公开(公告)日：2021-07-29

    申请号：US17018324

    申请日：2020-09-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ae-Nee JANG ,  Inhyo HWANG

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

    Abstract: A semiconductor device includes a first package, and a second package stacked on the first package. Each of the first and second packages includes a first redistribution substrate having a first redistribution pattern, a first semiconductor chip on the first redistribution substrate and connected to the first redistribution pattern, a first molding layer covering the first semiconductor chip on the first redistribution substrate, a first through-electrode penetrating the first molding layer so as to be connected to the first redistribution pattern, and a second through-electrode penetrating the first molding layer and not connected to the first redistribution pattern. The first redistribution pattern of the second package is electrically connected to the second through-electrode of the first package.

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