公开(公告)号：US09025366B2

公开(公告)日：2015-05-05

申请号：US14040595

申请日：2013-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Park ,  Ilguy Jung

IPC: G11C11/00 ,  G11C11/16 ,  G06F13/00

CPC classification number: G11C11/1675 ,  G06F8/61 ,  G06F9/4406 ,  G06F13/00 ,  G11C11/1653 ,  G11C11/1659

Abstract: A main memory system is provided which includes a nonvolatile memory including a first memory area designated to store an operating system program and a second memory area designated to store user data; and a memory controller configured to control the nonvolatile memory such that the operating system program is loaded onto the second memory area from the first memory area. The nonvolatile memory may be one of a phase change RAM, a resistive RAM, and a magnetic RAM.

Abstract translation: 提供一种主存储器系统，其包括非易失性存储器，包括被指定为存储操作系统程序的第一存储区域和指定用于存储用户数据的第二存储区域; 以及存储器控制器，其被配置为控制所述非易失性存储器，使得所述操作系统程序从所述第一存储区域加载到所述第二存储器区域。 非易失性存储器可以是相变RAM，电阻RAM和磁性RAM中的一个。

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11610624B2

公开(公告)日：2023-03-21

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

公开(公告)号：US20220215871A1

公开(公告)日：2022-07-07

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US09342257B2

公开(公告)日：2016-05-17

申请号：US14040968

申请日：2013-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-jin Park ,  Ilguy Jung

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/02 ,  G06F21/79

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0671 ,  G06F12/0238 ,  G06F21/79 ,  G06F2212/2024 ,  G06F2212/7201 ,  G06F2221/2143

Abstract: Provided are a computer system and a method of controlling the same. The computer system includes: a central processing unit (CPU) configured to drive an application program; and a main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU. The main memory includes: a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the data; a memory controller configured to control the nonvolatile memory; and a memory manager configured to read the address information from the second memory area and delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller.

Abstract translation: 提供一种计算机系统及其控制方法。 计算机系统包括：配置成驱动应用程序的中央处理单元（CPU） 以及主存储器，被配置为向CPU提供用于驱动应用程序的存储空间并存储CPU的处理结果。 主存储器包括：非易失性存储器，包括被配置为存储数据的第一存储器区域和被配置为存储数据的地址信息的第二存储器区域; 配置成控制非易失性存储器的存储器控​​制器; 以及存储器管理器，被配置为响应于来自CPU的数据删除命令和存储器控制器的控制，根据读取的地址信息从第二存储器区域读取地址信息并删除存储在第一区域中的数据。