公开(公告)号：US20140097448A1

公开(公告)日：2014-04-10

申请号：US13868490

申请日：2013-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woong-je SUNG ,  Chang-yong UM ,  Jai-kwang SHIN

IPC: H01L27/088 ,  H01L21/8232 ,  H01L21/82

CPC classification number: H01L27/088 ,  H01L21/0455 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/8213 ,  H01L21/8232 ,  H01L29/7827

Abstract: A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer.

Abstract translation: 半导体器件包括漂移层，其包括在半导体衬底上形成的沟槽。 漂移层中的阱与沟槽的边缘重叠，并且在该重叠边缘区域形成至少一个栅电极。 漂移层和半导体可以掺杂第一类型的杂质，并且阱可以掺杂第二类型的杂质。 通过这种布置，可以在漂移层中形成改进的载流子分布。

公开(公告)号：US20140197479A1

公开(公告)日：2014-07-17

申请号：US13960333

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yong UM ,  Jai-kwang SHIN

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/2815 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803

Abstract: A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type).

Abstract translation: 半导体器件可以包括具有掺杂到第一导电类型的漂移区的衬底。 可以将沟槽蚀刻到衬底的上表面中。 栅极可以沿着沟槽的侧壁布置。 栅极氧化物层可以在沟槽的侧壁和栅极之间以及沟槽的底表面和栅极之间。 第一导电类型的第一源区可以在衬底的上表面上。 第一导电类型的第二源极区可以在沟槽的底表面上。 第一阱区可以在第一源极区域和漂移区域之间，第二阱区域可以在第二源极区域和漂移区域之间，第一和第二阱区域被掺杂到第二导电类型（与第一源区域 导电型）。