公开(公告)号：US20190287953A1

公开(公告)日：2019-09-19

申请号：US16170469

申请日：2018-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon Hee MOON ,  Myung Sam KANG ,  Young Gwan KO ,  Chang Bae LEE ,  Jin Su KIM

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/053 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.

公开(公告)号：US20210313276A1

公开(公告)日：2021-10-07

申请号：US17353074

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon LEE ,  Myung Sam KANG ,  Young Gwan KO ,  Young Chan KO ,  Chang Bae LEE

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/66 ,  H01L21/48 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13

Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.

公开(公告)号：US20230260919A1

公开(公告)日：2023-08-17

申请号：US18141568

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon LEE ,  Myung Sam KANG ,  Young Gwan KO ,  Young Chan KO ,  Chang Bae LEE

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/66 ,  H01L21/48 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L24/05 ,  H01L23/3135 ,  H01L24/24 ,  H01L23/5386 ,  H01L25/16 ,  H01L23/66 ,  H01L24/19 ,  H01L21/486 ,  H01L24/82 ,  H01L21/4857 ,  H01L21/4853 ,  H01L23/552 ,  H01Q1/38 ,  H01L23/13 ,  H01L2924/3025 ,  H01L2223/6677 ,  H01L2223/6616 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/82101

Abstract: A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.