Abstract:
A semiconductor device includes an integrator, a successive approximation register analog-to-digital converter (SAR ADC) and a residue capacitor. The integrator is configured to receive a signal and generate a first analog signal during a first operation mode using a capacitor module comprising one or more capacitors. The SAR ADC is configured to receive the first analog signal, convert the first analog signal into a first digital signal using the capacitor module, and generate a first residue signal in a second operation mode. The residue capacitor is connected to the capacitor module in parallel, and is configured to receive the first residue signal in the second operation mode and provide the first residue signal to the integrator in the first operation mode.
Abstract translation:半导体器件包括积分器,逐次逼近寄存器模数转换器(SAR ADC)和残留电容器。 积分器被配置为在使用包括一个或多个电容器的电容器模块的第一操作模式期间接收信号并产生第一模拟信号。 SAR ADC被配置为接收第一模拟信号,使用电容器模块将第一模拟信号转换为第一数字信号,并在第二操作模式中产生第一残留信号。 剩余电容器并联连接到电容器模块,并且被配置为在第二操作模式下接收第一残留信号,并且在第一操作模式中向积分器提供第一残留信号。
Abstract:
A touch sensing device includes a touch panel and a receiving unit. The touch panel generates first to third receiving signals corresponding to a touch occurring at the touch sensing device. The receiving unit is connected to the touch panel through first to third receiving lines to receive the first to third receiving signals through the first to third receiving lines, respectively. The receiving unit includes a differential signal generator for excluding a first common signal common to the first and second receiving signals from each of the first and second receiving signals to generate first differential signals when a first touch sensing operation is performed. The differential signal generator excludes a second common signal common to the second and third receiving signals from each of the second and third receiving signals to generate second differential signals when a second touch sensing operation is performed.
Abstract:
An apparatus includes a sample holding circuit, a comparator, a digital-to-analog converter, a clock generator, a successive approximation logic circuit, and a background calibration circuit. The apparatus converts an analog signal into digital data based on an asynchronous clock signal. The clock signal follows the number of clocks in a converting operation section through a background calibration scheme.