公开(公告)号：US09553121B2

公开(公告)日：2017-01-24

申请号：US14835284

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki Sekikawa ,  Hidenori Sato ,  Yotaro Goto ,  Takuya Maruyama ,  Masaaki Shinohara

IPC: H01L21/4763 ,  H01L27/146 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/66 ,  H01L23/532

CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。

公开(公告)号：US10566367B2

公开(公告)日：2020-02-18

申请号：US15900383

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Yotaro Goto ,  Takeshi Kamino ,  Fumitoshi Takahashi

IPC: H01L27/146

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n−− type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.

公开(公告)号：US10297624B2

公开(公告)日：2019-05-21

申请号：US15934484

申请日：2018-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Kunikiyo ,  Hidenori Sato ,  Yotaro Goto ,  Fumitoshi Takahashi

IPC: H01L27/12 ,  H01L27/146

Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

公开(公告)号：US12159934B2

公开(公告)日：2024-12-03

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai ,  Yotaro Goto

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US10566373B2

公开(公告)日：2020-02-18

申请号：US15983029

申请日：2018-05-17

Applicant: Renesas Electronics Corporation

Inventor： Yotaro Goto ,  Tatsuya Kunikiyo ,  Hidenori Sato

IPC: H01L31/062 ,  H01L27/146 ,  H01L23/00

Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.

公开(公告)号：US09773830B2

公开(公告)日：2017-09-26

申请号：US15017573

申请日：2016-02-05

Applicant: Renesas Electronics Corporation

Inventor： Yotaro Goto

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14683

Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.

公开(公告)号：US11527632B2

公开(公告)日：2022-12-13

申请号：US17316017

申请日：2021-05-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yotaro Goto ,  Katsumi Eikyu ,  Yoshihiro Nomura

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

公开(公告)号：US10115751B2

公开(公告)日：2018-10-30

申请号：US15365344

申请日：2016-11-30

Applicant: Renesas Electronics Corporation

Inventor： Takeshi Kamino ,  Yotaro Goto

IPC: H01L27/146

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.

公开(公告)号：US10032820B2

公开(公告)日：2018-07-24

申请号：US15189303

申请日：2016-06-22

Applicant: Renesas Electronics Corporation

Inventor： Yotaro Goto

IPC: H01L27/146

Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film.Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.

公开(公告)号：US20180308884A1

公开(公告)日：2018-10-25

申请号：US15900383

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Yotaro Goto ,  Takeshi Kamino ,  Fumitoshi Takahashi

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n−− type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.