公开(公告)号：US10297624B2

公开(公告)日：2019-05-21

申请号：US15934484

申请日：2018-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Kunikiyo ,  Hidenori Sato ,  Yotaro Goto ,  Fumitoshi Takahashi

IPC: H01L27/12 ,  H01L27/146

Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

公开(公告)号：US10566373B2

公开(公告)日：2020-02-18

申请号：US15983029

申请日：2018-05-17

Applicant: Renesas Electronics Corporation

Inventor： Yotaro Goto ,  Tatsuya Kunikiyo ,  Hidenori Sato

IPC: H01L31/062 ,  H01L27/146 ,  H01L23/00

Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.

公开(公告)号：US10978505B2

公开(公告)日：2021-04-13

申请号：US16278941

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidenori Sato ,  Koji Iizuka ,  Takeshi Kamino

IPC: H01L27/14 ,  H01L27/146 ,  H01L23/00

Abstract: A hybrid-bonding-type solid-state imaging device is provided that prevents moisture from entering through the bonded interface and other areas. The solid-state imaging device includes a first interconnect structure over a sensor substrate and a second interconnect structure over a logic substrate, and the first and second interconnect structures are bonded together. At the bonded surface between the first and second interconnect structures, bonding pads formed in the first interconnect structure are bonded to bonding pads formed in the second interconnect structure. Eighth layer portions of a first seal ring formed in the first interconnect structure are bonded to eighth layer portions of a second seal ring formed in the second interconnect structure.

公开(公告)号：US09553121B2

公开(公告)日：2017-01-24

申请号：US14835284

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki Sekikawa ,  Hidenori Sato ,  Yotaro Goto ,  Takuya Maruyama ,  Masaaki Shinohara

IPC: H01L21/4763 ,  H01L27/146 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/66 ,  H01L23/532

CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。