公开(公告)号：US20170221803A1

公开(公告)日：2017-08-03

申请号：US15368640

申请日：2016-12-04

Applicant: Renesas Electronics Corporation

Inventor： Katsuhito KAMACHI ,  Hideaki TAMIMOTO

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49555 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05553 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/7855 ,  H01L2224/78704 ,  H01L2224/7898 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

公开(公告)号：US20180019189A1

公开(公告)日：2018-01-18

申请号：US15711641

申请日：2017-09-21

Applicant: Renesas Electronics Corporation

Inventor： Katsuhito KAMACHI ,  Hideaki TAMIMOTO

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49555 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05553 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/7855 ,  H01L2224/78704 ,  H01L2224/7898 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

公开(公告)号：US20130244381A1

公开(公告)日：2013-09-19

申请号：US13795374

申请日：2013-03-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhito KAMACHI ,  Takanori OKITA

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/4842 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2224/83205

Abstract: A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE1c of a first lead, a tip portion LE2c of a second lead, and a tip portion LE3c of a third lead by using a spanking die SDM1, the tip portion LE1c of the first lead, the tip portion LE2c of the second lead, and the tip portion LE3c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU1, and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD1 and a flat pressing surface of the upper die SU1.

Abstract translation: 提高了包括功率晶体管的半导体器件的制造成品率。 当使用打屁股模具SDM1形成第一引线的尖端部分LE1c，第二引线的尖端部分LE2c和第三引线的尖端部分LE3c时，第一引线的尖端部分LE1c，尖端部分LE2c的尖端部分LE2c 第二引线和第三引线的尖端部分LE3c被设置在下模具SD1的按压表面上的突出部分的上表面和设置在上模具的按压表面中的凹槽部分的底表面 SU1，第二引线的弯曲部分和第三引线的弯曲部分被下模具SD1的平坦的按压面和上模具SU1的平坦的按压面按压。