公开(公告)号：US20150249145A1

公开(公告)日：2015-09-03

申请号：US14634736

申请日：2015-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hiromasa YOSHIMORI ,  Hirofumi TOKITA

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/3105

CPC classification number: H01L27/1157 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.

Abstract translation: 提供了具有改进的性能的半导体器件。 在半导体衬底上，通过第一绝缘膜形成虚拟控制栅电极。 在半导体衬底上，用于存储单元的存储栅电极经由具有内部电荷存储部分的第二绝缘膜形成，以便与虚拟控制栅电极相邻。 此时，存储栅电极的高度被调节为低于虚拟控制栅电极的高度。 然后，形成第三绝缘膜，以覆盖虚拟控制栅电极和存储栅电极。 然后，对第三绝缘膜进行抛光以露出虚拟控制栅电极。 此时，存储栅电极不露出。 然后，去除虚拟控制栅电极并用金属栅电极代替。

公开(公告)号：US20140319618A1

公开(公告)日：2014-10-30

申请号：US14329294

申请日：2014-07-11

Applicant: Renesas Electronics Corporation

Inventor： Hiromasa YOSHIMORI ,  Hirofumi Shinohara ,  Toshiaki Iwamatsu

IPC: H01L29/51 ,  H01L27/088

CPC classification number: H01L29/512 ,  H01L21/8234 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484

Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.

Abstract translation: 提高了半导体器件的性能。 该器件包括第一MISFET，其中将铪添加到包括氮氧化硅的第一栅极绝缘膜的栅极电极侧，以及第二MISFET，其中在包括氮氧化硅的第二栅极绝缘膜的栅极电极侧添加铪。 将第二MISFET的第二栅极绝缘膜中的铪浓度设定为小于第一MISFET的第一栅极绝缘膜中的铪浓度; 并且将第二MISFET的第二栅极绝缘膜中的氮浓度设定为小于第一MISFET的第一栅极绝缘膜中的氮浓度。 结果，第二MISFET的阈值电压被调整为小于第一MISFET的阈值电压。

公开(公告)号：US20130161753A1

公开(公告)日：2013-06-27

申请号：US13693351

申请日：2012-12-04

Applicant: Renesas Electronics Corporation

Inventor： Hiromasa YOSHIMORI ,  Hirofumi Shinohara ,  Toshiaki Iwamatsu

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/8234 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484

Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.

Abstract translation: 提高了半导体器件的性能。 该器件包括第一MISFET，其中将铪添加到包括氮氧化硅的第一栅极绝缘膜的栅极电极侧，以及第二MISFET，其中在包括氮氧化硅的第二栅极绝缘膜的栅极电极侧添加铪。 将第二MISFET的第二栅极绝缘膜中的铪浓度设定为小于第一MISFET的第一栅极绝缘膜中的铪浓度; 并且将第二MISFET的第二栅极绝缘膜中的氮浓度设定为小于第一MISFET的第一栅极绝缘膜中的氮浓度。 结果，第二MISFET的阈值电压被调整为小于第一MISFET的阈值电压。

公开(公告)号：US20170018556A1

公开(公告)日：2017-01-19

申请号：US15277996

申请日：2016-09-27

Applicant: Renesas Electronics Corporation

Inventor： Hiromasa YOSHIMORI ,  Hirofumi TOKITA

IPC: H01L27/115 ,  H01L29/06 ,  H01L23/535 ,  H01L29/36 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.

Abstract translation: 提供了具有改进的性能的半导体器件。 在半导体衬底上，通过第一绝缘膜形成虚拟控制栅电极。 在半导体衬底上，用于存储单元的存储栅电极经由具有内部电荷存储部分的第二绝缘膜形成，以便与虚拟控制栅电极相邻。 此时，存储栅电极的高度被调节为低于虚拟控制栅电极的高度。 然后，形成第三绝缘膜，以覆盖虚拟控制栅电极和存储栅电极。 然后，对第三绝缘膜进行抛光以露出虚拟控制栅电极。 此时，存储栅电极不露出。 然后，去除虚拟控制栅电极并用金属栅电极代替。