公开(公告)号：US08099269B2

公开(公告)日：2012-01-17

申请号：US11869522

申请日：2007-10-09

Applicant: Rasit O. Topaloglu ,  Jung-Suk Goo

Inventor： Rasit O. Topaloglu ,  Jung-Suk Goo

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation.

Abstract translation: 本发明是用于模拟电路的老化处理的方法和系统。 采用两步法，其中在第一模拟步骤中，进行仿真以获得原始电路的节点电压，并将节点电压存储在文件中。 在第二步中，在电路的晶体管被​​包含老化模型的老化子电路代替，并且更新初始节点电压之后，继续进行仿真。 脚本用于使用从第一步存储在文件中的节点电压来设置老化模型的偏置电压输入。 使用更准确的老化模型的偏置电压输入，进行老化模拟以计算电路退化。

公开(公告)号：US20130027127A1

公开(公告)日：2013-01-31

申请号：US13194695

申请日：2011-07-29

Applicant: Rasit O. Topaloglu

Inventor： Rasit O. Topaloglu

IPC: H01L25/00

CPC classification number: H01L25/162 ,  H01L23/66 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system is provided that includes a circuit function in and on a surface of a semiconductor substrate. First and second portions of an inductor overlie the surface of the semiconductor substrate and each is coupled to the first circuit function. A third portion of the inductor is positioned on a second substrate. A first through substrate via (TSV) extends through the semiconductor substrate and electrically couples the first portion to the third portion and a second TSV extends through the semiconductor substrate and electrically couples the second portion to the third portion.

Abstract translation: 提供了一种集成电路系统，其包括在半导体衬底的表面中和之上的电路功能。 电感器的第一和第二部分覆盖在半导体衬底的表面上，并且每个部分耦合到第一电路功能。 电感器的第三部分位于第二衬底上。 第一贯穿衬底通孔（TSV）延伸穿过半导体衬底并将第一部分电耦合到第三部分，并且第二TSV延伸穿过半导体衬底并将第二部分电耦合到第三部分。

公开(公告)号：US07671418B2

公开(公告)日：2010-03-02

申请号：US11855733

申请日：2007-09-14

Applicant: Rasit O. Topaloglu

Inventor： Rasit O. Topaloglu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7843 ,  H01L29/785 ,  H01L29/78648

Abstract: Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer.

Abstract translation: 多个栅极晶体管设置有双应力层，用于增加沟道迁移率和增强的有效和饱和驱动电流。 实施例包括晶体管，其包括底栅下的第一应力层和覆盖在顶栅上的第二应力层。 实施例还包括具有底部栅极在第一应力层内或通过第一应力层的晶体管。 方法包括在其上具有底部氧化物层的衬底上依次沉积应力氮化硅，氮化物，氧化物，非晶硅和氧化物层，图案化以限定沟道长度，沉积顶部氮化物层，在受应力的氮化硅层上图案化停止， 去除非晶硅层，通过衬底中的窗口外延生长硅以形成源极，漏极和沟道区域，掺杂，去除沉积的氮化物和氧化物层，生长栅极氧化物，沉积多晶硅以形成栅极，生长隔离氧化物，以及 沉积顶部应力层。

公开(公告)号：US09159711B2

公开(公告)日：2015-10-13

申请号：US13194695

申请日：2011-07-29

Applicant: Rasit O. Topaloglu

Inventor： Rasit O. Topaloglu

IPC: H05K1/00 ,  H01F5/00 ,  H01F27/28 ,  H01L25/16 ,  H01L23/66

CPC classification number: H01L25/162 ,  H01L23/66 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system is provided that includes a circuit function in and on a surface of a semiconductor substrate. First and second portions of an inductor overlie the surface of the semiconductor substrate and each is coupled to the first circuit function. A third portion of the inductor is positioned on a second substrate. A first through substrate via (TSV) extends through the semiconductor substrate and electrically couples the first portion to the third portion and a second TSV extends through the semiconductor substrate and electrically couples the second portion to the third portion.

Abstract translation: 提供了一种集成电路系统，其包括在半导体衬底的表面中和之上的电路功能。 电感器的第一和第二部分覆盖在半导体衬底的表面上，并且每个部分耦合到第一电路功能。 电感器的第三部分位于第二衬底上。 第一贯穿衬底通孔（TSV）延伸穿过半导体衬底并将第一部分电耦合到第三部分，并且第二TSV延伸穿过半导体衬底并将第二部分电耦合到第三部分。

公开(公告)号：US08219994B2

公开(公告)日：2012-07-10

申请号：US12256703

申请日：2008-10-23

Applicant: Rasit O. Topaloglu

Inventor： Rasit O. Topaloglu

IPC: G06F9/46

CPC classification number: G06F9/5094 ,  Y02D10/22

Abstract: A data processing device assigns tasks to processor cores in a more distributed fashion. In one embodiment, the data processing device can schedule tasks for execution amongst the processor cores in a pseudo-random fashion. In another embodiment, the processor core can schedule tasks for execution amongst the processor cores based on the relative amount of historical utilization of each processor core. In either case, the effects of bias temperature instability (BTI) resulting from task execution are distributed among the processor cores in a more equal fashion than if tasks are scheduled according to a fixed order. Accordingly, the useful lifetime of the processor unit can be extended.

Abstract translation: 数据处理设备以更分散的方式将任务分配给处理器核心。 在一个实施例中，数据处理设备可以以伪随机方式调度处理器核心之间的执行任务。 在另一个实施例中，处理器核可以基于每个处理器核的历史利用的相对量来调度在处理器核之间执行的任务。 在任一情况下，任务执行产生的偏置温度不稳定性（BTI）的影响以与按照固定顺序调度任务相等的方式分配在处理器核心之间。 因此，可以延长处理器单元的有用寿命。

公开(公告)号：US20100107166A1

公开(公告)日：2010-04-29

申请号：US12256703

申请日：2008-10-23

Applicant: Rasit O. Topaloglu

Inventor： Rasit O. Topaloglu

IPC: G06F9/46

CPC classification number: G06F9/5094 ,  Y02D10/22

Abstract: A data processing device assigns tasks to processor cores in a more distributed fashion. In one embodiment, the data processing device can schedule tasks for execution amongst the processor cores in a pseudo-random fashion. In another embodiment, the processor core can schedule tasks for execution amongst the processor cores based on the relative amount of historical utilization of each processor core. In either case, the effects of bias temperature instability (BTI) resulting from task execution are distributed among the processor cores in a more equal fashion than if tasks are scheduled according to a fixed order. Accordingly, the useful lifetime of the processor unit can be extended.

Abstract translation: 数据处理设备以更分散的方式将任务分配给处理器核心。 在一个实施例中，数据处理设备可以以伪随机方式调度处理器核心之间的执行任务。 在另一个实施例中，处理器核可以基于每个处理器核的历史利用的相对量来调度在处理器核之间执行的任务。 在任一情况下，任务执行产生的偏置温度不稳定性（BTI）的影响以与按照固定顺序调度任务相等的方式分配在处理器核心之间。 因此，可以延长处理器单元的有用寿命。