公开(公告)号：US20080133820A1

公开(公告)日：2008-06-05

申请号：US11607556

申请日：2006-11-30

Applicant: Ramkarthik Ganesan ,  Saad Monasa ,  William Low

Inventor： Ramkarthik Ganesan ,  Saad Monasa ,  William Low

IPC: G06F12/00

CPC classification number: G11C8/10 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/32

Abstract: A DDR non-volatile memory providing Double Data Rate (DDR) operation by decoding an address received from an external processor at a DDR interface to provide a command to store data in page buffers. The data received from the external processor at the DDR interface is transferred to page buffers based on the command. A command issued by an internal microcontroller transfers data stored in the page buffers to non-volatile storage.

Abstract translation: 一种DDR非易失性存储器，通过对在DDR接口处的外部处理器接收到的地址进行解码来提供双数据速率（DDR）操作，以提供在页面缓冲器中存储数据的命令。 根据该命令将从DDR接口的外部处理器接收的数据传送到页缓冲区。 由内部微控制器发出的命令将存储在页缓冲器中的数据传送到非易失性存储器。

公开(公告)号：US20050183452A1

公开(公告)日：2005-08-25

申请号：US10785808

申请日：2004-02-24

Applicant: Paul Hahn ,  Phillip Ritchie ,  Jame Yao ,  Rong-Jwyn Lee ,  Anthony Eaton ,  William Low

Inventor： Paul Hahn ,  Phillip Ritchie ,  Jame Yao ,  Rong-Jwyn Lee ,  Anthony Eaton ,  William Low

IPC: F25J1/02 ,  F25J3/02 ,  F25J1/00 ,  F25J3/00

CPC classification number: F25J3/0257 ,  F25J1/0022 ,  F25J1/004 ,  F25J1/0052 ,  F25J1/021 ,  F25J1/0261 ,  F25J1/0265 ,  F25J3/0209 ,  F25J3/0233 ,  F25J3/0295 ,  F25J2200/08 ,  F25J2200/70 ,  F25J2210/06 ,  F25J2215/04 ,  F25J2220/62 ,  F25J2220/64 ,  F25J2245/02 ,  F25J2270/12 ,  F25J2270/60 ,  F25J2280/02 ,  F25J2290/30 ,  F25J2290/42 ,  Y10S62/927

Abstract: Natural gas liquefaction system employing an enhanced nitrogen removal system capable of removing nitrogen from a relatively warm natural gas stream.

Abstract translation: 天然气液化系统采用能够从相对温暖的天然气流中除去氮的增强除氮系统。

公开(公告)号：US06628243B1

公开(公告)日：2003-09-30

申请号：US09458263

申请日：1999-12-09

Applicant: George Lyons ,  William Low

Inventor： George Lyons ,  William Low

IPC: G09G500

CPC classification number: G09G5/006 ,  G06F3/1431 ,  G09G5/363 ,  G09G5/395

Abstract: Multiple independent images are presented on multiple display devices by driving the display devices with a common set of control signals and a multiplexed set of data signals that convey information representing interleaved components of each independent image. In a preferred embodiment, a unique clock signal is provided to each respective display device that is aligned with the interleaved components of the image to be presented by that respective display. The control, data and clock signals may be obtained by multiplexing control and data signals received from display pipeline circuits, or by generating the, signals using a composite circuit that implements the features of two or more multiplexed display pipeline circuits.

Abstract translation: 通过用共同的一组控制信号驱动显示设备和传送表示每个独立图像的交织分量的信息的多路复用数据信号组，在多个显示设备上呈现多个独立图像。 在优选实施例中，向每个相应的显示设备提供唯一的时钟信号，其与由相应显示器呈现的图像的交织分量对齐。 控制，数据和时钟信号可以通过复用从显示流水线电路接收的控制和数据信号，或者通过使用实现两个或更多个多路复用显示管道电路的特征的复合电路生成信号来获得。

公开(公告)号：US5758135A

公开(公告)日：1998-05-26

申请号：US721087

申请日：1996-09-24

Applicant: David M. Tucker ,  William Low

Inventor： David M. Tucker ,  William Low

IPC: G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/12 ,  G09G5/18 ,  G09G5/36 ,  G09G5/391 ,  H04N5/66 ,  G06F1/10

CPC classification number: G09G5/005 ,  G09G3/3611 ,  G09G5/366 ,  G09G2310/0232 ,  G09G2340/04 ,  G09G5/006 ,  G09G5/18

Abstract: A clocking system including a line clock system for generating normal line clock pulses to the digital display during the period when the image is being rendered and for generating fast line clock pulses to the digital display during the vertical blanking period to address the otherwise unaddressed vertical region. The clocking system further includes a pixel clock system for generating normal pixel clock pulses to the digital display during the period when the image is being rendered and for generating fast pixel clock pulses to the digital display during the horizontal and vertical blanking periods to address the otherwise unaddressed horizontal and vertical regions.

Abstract translation: 一种时钟系统，包括线时钟系统，用于在图像呈现期间在数字显示器上产生法线行时钟脉冲，并且在垂直消隐期间产生快速线时钟脉冲到数字显示器，以寻址另外未被解决的垂直区域 。 时钟系统还包括像素时钟系统，用于在图像渲染期间产生正常像素时钟脉冲到数字显示器，并且在水平和垂直消隐期间产生到数字显示器的快速像素时钟脉冲以寻址否则 未处理的水平和垂直区域。