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    DDR flash implementation with row buffer interface to legacy flash functions
    1.
    发明申请
    DDR flash implementation with row buffer interface to legacy flash functions 审中-公开
    DDR闪存实现与行缓冲区接口传统的Flash功能

    公开(公告)号：US20080133820A1

    公开(公告)日：2008-06-05

    申请号：US11607556

    申请日：2006-11-30

    申请人： Ramkarthik Ganesan ,  Saad Monasa ,  William Low

    发明人： Ramkarthik Ganesan ,  Saad Monasa ,  William Low

    IPC分类号： G06F12/00

    CPC分类号： G11C8/10 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/32

    摘要： A DDR non-volatile memory providing Double Data Rate (DDR) operation by decoding an address received from an external processor at a DDR interface to provide a command to store data in page buffers. The data received from the external processor at the DDR interface is transferred to page buffers based on the command. A command issued by an internal microcontroller transfers data stored in the page buffers to non-volatile storage.

    摘要翻译： 一种DDR非易失性存储器，通过对在DDR接口处的外部处理器接收到的地址进行解码来提供双数据速率（DDR）操作，以提供在页面缓冲器中存储数据的命令。 根据该命令将从DDR接口的外部处理器接收的数据传送到页缓冲区。 由内部微控制器发出的命令将存储在页缓冲器中的数据传送到非易失性存储器。

    Burst suspend and resume with computer memory
    8.
    发明授权
    Burst suspend and resume with computer memory 失效
    爆破暂停和恢复与计算机内存

    公开(公告)号：US06618790B1

    公开(公告)日：2003-09-09

    申请号：US09675288

    申请日：2000-09-29

    申请人： Sanjay S. Talreja ,  Lance W. Dover ,  Ramkarthik Ganesan ,  Ramadurai Rajagopal

    发明人： Sanjay S. Talreja ,  Lance W. Dover ,  Ramkarthik Ganesan ,  Ramadurai Rajagopal

    IPC分类号： G06F1200

    CPC分类号： G06F13/28

    摘要： A burst transfer operation with a memory device can be suspended and resumed without having to provide the current memory address when it is resumed. A chip enable signal to the memory device can be deasserted to initiate the suspend operation and place the memory device in a low power standby mode. When the chip enable signal is reasserted, the memory device can be reactivated and the burst transfer can continue where it stopped, without any setup commands. The current address counter and other bus transfer parameters can be saved within the memory device during the suspend operation. When the suspend operation is terminated by reasserting the chip enable signal, the memory device can resume the transfer using the saved parameters.

    摘要翻译： 具有存储器件的突发传送操作可以被暂停并恢复，而不必在恢复时提供当前存储器地址。 可以将对存储器件的芯片使能信号置低，以启动挂起操作并将存储器件置于低功率待机模式。 当重新使能芯片使能信号时，可以重新激活存储器件，并且在没有任何设置命令的情况下，突发传输可以在其停止的位置继续。 在挂起操作期间，当前地址计数器和其他总线传输参数可以保存在存储器件中。 当通过重新启动芯片使能信号来终止暂停操作时，存储器件可以使用保存的参数来恢复传输。

    Method and apparatus for reducing stress across capacitors used in integrated circuits
    9.
    再颁专利
    Method and apparatus for reducing stress across capacitors used in integrated circuits 有权
    用于减少集成电路中使用的电容器的应力的方法和装置

    公开(公告)号：USRE41217E1

    公开(公告)日：2010-04-13

    申请号：US10678055

    申请日：2003-10-02

    申请人： Ramkarthik Ganesan ,  Owen W. Jungroth

    发明人： Ramkarthik Ganesan ,  Owen W. Jungroth

    IPC分类号： H02M3/18

    CPC分类号： H02M3/073

    摘要： A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors. The voltage level of the middle node is set to a third voltage level when the integrated circuit is placed in the first power state such that the voltage level between the first and middle nodes does not exceed the breakdown voltage of the first capacitor and the voltage level between the middle and second nodes does not exceed the breakdown voltage of the second capacitor.

    摘要翻译： 一种用于控制耦合在集成电路的第一节点和第二节点之间的电容器上的电压电平的方法，装置和系统，使得这些电容器两端的电压电平将不会超过这些电容器的击穿电压限制。 当集成电路分别从第二功率状态转换到第一功率状态时，集成电路的第一和第二节点之间的电压电平可以从第二电压电平变化到第一电压电平。 第一电容器和第二电容器串联连接在集成电路的第一和第二节点之间，形成第一和第二电容器之间的中间节点。 当集成电路处于第一功率状态时，中间节点的电压电平被设置为第三电压电平，使得第一和中间节点之间的电压电平不超过第一电容器的击穿电压和电压电平 在中间和第二节点之间不超过第二电容器的击穿电压。