公开(公告)号：US10777569B2

公开(公告)日：2020-09-15

申请号：US16404095

申请日：2019-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto Omizu ,  Takashi Hashimoto ,  Hideaki Yamakoshi

IPC: H01L21/3065 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/28

Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

公开(公告)号：US10026744B2

公开(公告)日：2018-07-17

申请号：US15672909

申请日：2017-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/112 ,  H01L27/11563

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US09196363B2

公开(公告)日：2015-11-24

申请号：US14584533

申请日：2014-12-29

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi ,  Daisuke Okada

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/10

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/42328

Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.

Abstract translation: 提供了具有改进的性能的半导体器件。 半导体器件包括闪速存储器的存储单元。 每个存储单元包括用于写入/擦除具有由浮置栅电极的一部分形成的栅电极的数据的电容器元件和用于读取具有由浮置栅电极的另一部分形成的栅电极的数据的MISFET。 用于写入/擦除数据的电容器元件具有具有相反导电类型的p型半导体区域和n型半导体区域。 用于写入/擦除数据的电容器元件中的栅极长度方向上的浮栅电极的长度小于用于读取数据的MISFET中的栅极长度方向上的浮栅电极的长度。

公开(公告)号：US10325899B2

公开(公告)日：2019-06-18

申请号：US15880212

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Keiichi Maekawa ,  Hideaki Yamakoshi ,  Shinichiro Abe ,  Hideki Makiyama ,  Tetsuya Yoshida ,  Yuto Omizu

IPC: G11C16/04 ,  H01L27/02 ,  G11C16/12 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11573

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

公开(公告)号：US20180366556A1

公开(公告)日：2018-12-20

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L21/8239

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US20150187782A1

公开(公告)日：2015-07-02

申请号：US14584533

申请日：2014-12-29

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi ,  Daisuke Okada

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/42328

Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.

Abstract translation: 提供了具有改进的性能的半导体器件。 半导体器件包括闪速存储器的存储单元。 每个存储单元包括用于写入/擦除具有由浮置栅电极的一部分形成的栅电极的数据的电容器元件和用于读取具有由浮置栅电极的另一部分形成的栅电极的数据的MISFET。 用于写入/擦除数据的电容器元件具有具有相反导电类型的p型半导体区域和n型半导体区域。 用于写入/擦除数据的电容器元件中的栅极长度方向上的浮栅电极的长度小于用于读取数据的MISFET中的栅极长度方向上的浮栅电极的长度。

公开(公告)号：US08994092B2

公开(公告)日：2015-03-31

申请号：US14103829

申请日：2013-12-11

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi

IPC: H01L27/115 ,  G11C16/00

CPC classification number: H01L27/11524 ,  G11C16/00 ,  G11C16/0408

Abstract: A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, −7 V is applied to the drain of a selected nonvolatile memory cell, −8 V is applied to the gate electrode of the selection transistor, and further −3 V is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed. Thereby, a selected nonvolatile memory cell is discriminated from an unselected nonvolatile memory cell.

Abstract translation: 提供了包括具有高性能和高可靠性的非易失性存储单元的半导体器件。 非易失性存储单元包括第一n阱，在第一方向上与第一n阱分离的第二n阱，形成在第一n阱中的选择晶体管，形成为与 在平面图中的第一n阱和第二n阱的一部分，以及形成在浮置栅电极的两侧的第二n阱中的n导电型半导体区域。 在写入操作中，-7V被施加到所选择的非易失性存储单元的漏极，-8V施加到选择晶体管的栅电极，并且还向该n导电型半导体区域施加-3V 获得更高的写入速度。 由此，从未选择的非易失性存储单元中识别选定的非易失性存储单元。

公开(公告)号：US11145744B2

公开(公告)日：2021-10-12

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro Abe ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/12 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US10651188B2

公开(公告)日：2020-05-12

申请号：US16520758

申请日：2019-07-24

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/11568 ,  G11C11/40 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

公开(公告)号：US10483273B2

公开(公告)日：2019-11-19

申请号：US16012362

申请日：2018-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/108 ,  H01L27/11563 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.