公开(公告)号：US20240170373A1

公开(公告)日：2024-05-23

申请号：US18483740

申请日：2023-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki TAMIMOTO ,  Masatoshi SUGIURA ,  Atsushi SAKAZAKI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L23/3121 ,  H01L23/49568 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48247 ,  H01L2224/49111

Abstract: An upper surface of a main portion of a die pad includes a first region overlapping a semiconductor chip, a second region arranged between a side and the first region, and a third region arranged between the first region and a connecting portion. In the upper surface of the main portion, each of a second trench length of a second trench arranged in the second region and a third trench length of a third trench arranged in the third region is larger than a first trench length of a first trench arranged in the connecting portion. Each of a second trench width of the second trench arranged in the second region and a third trench width of the third trench arranged in the third region is smaller than a first trench width of the first trench arranged in the connecting portion.

公开(公告)号：US20170221803A1

公开(公告)日：2017-08-03

申请号：US15368640

申请日：2016-12-04

Applicant: Renesas Electronics Corporation

Inventor： Katsuhito KAMACHI ,  Hideaki TAMIMOTO

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49555 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05553 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/7855 ,  H01L2224/78704 ,  H01L2224/7898 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

公开(公告)号：US20250096078A1

公开(公告)日：2025-03-20

申请号：US18808400

申请日：2024-08-19

Applicant: Renesas Electronics Corporation

Inventor： Hideaki TAMIMOTO

IPC: H01L23/495 ,  H01L23/31

Abstract: A first surface of a die pad has: a first region; a second region that includes points respectively overlapping with four corners of a semiconductor chip; and a third region that is located around the second region. Also, a plurality of grooves is formed in the die pad at the second region. Also, each of the plurality of grooves terminates at a position not reaching each of the first region and the third region. Also, the plurality of grooves includes: a plurality of first grooves each extending in an extending direction of one of two diagonal lines of the semiconductor chip; and a plurality of second grooves each extending in an extending direction of another one of the two diagonal lines. Also, in each of the plurality of first grooves is arranged so as to intersect with one or more of the plurality of second grooves.

公开(公告)号：US20230378032A1

公开(公告)日：2023-11-23

申请号：US18175805

申请日：2023-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke KITAICHI ,  Masatoshi SUGIURA ,  Hideaki TAMIMOTO ,  Takehiko MAEDA ,  Keita TAKADA ,  Yoshitaka KYOUGOKU

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H02M7/00

CPC classification number: H01L23/49562 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49513 ,  H01L24/48 ,  H01L23/3142 ,  H01L21/565 ,  H01L23/4952 ,  H01L23/49582 ,  H02M7/003 ,  H01L24/83 ,  H01L2224/48247 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L2924/30101 ,  H01L2924/13091 ,  H01L2224/83862

Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.

公开(公告)号：US20180019189A1

公开(公告)日：2018-01-18

申请号：US15711641

申请日：2017-09-21

Applicant: Renesas Electronics Corporation

Inventor： Katsuhito KAMACHI ,  Hideaki TAMIMOTO

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49555 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05553 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/7855 ,  H01L2224/78704 ,  H01L2224/7898 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.