公开(公告)号：US20240170373A1

公开(公告)日：2024-05-23

申请号：US18483740

申请日：2023-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki TAMIMOTO ,  Masatoshi SUGIURA ,  Atsushi SAKAZAKI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L23/3121 ,  H01L23/49568 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48247 ,  H01L2224/49111

Abstract: An upper surface of a main portion of a die pad includes a first region overlapping a semiconductor chip, a second region arranged between a side and the first region, and a third region arranged between the first region and a connecting portion. In the upper surface of the main portion, each of a second trench length of a second trench arranged in the second region and a third trench length of a third trench arranged in the third region is larger than a first trench length of a first trench arranged in the connecting portion. Each of a second trench width of the second trench arranged in the second region and a third trench width of the third trench arranged in the third region is smaller than a first trench width of the first trench arranged in the connecting portion.

公开(公告)号：US20190006268A1

公开(公告)日：2019-01-03

申请号：US15985957

申请日：2018-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masatoshi SUGIURA ,  Hiroi OKA

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/08 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.

公开(公告)号：US20230378032A1

公开(公告)日：2023-11-23

申请号：US18175805

申请日：2023-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke KITAICHI ,  Masatoshi SUGIURA ,  Hideaki TAMIMOTO ,  Takehiko MAEDA ,  Keita TAKADA ,  Yoshitaka KYOUGOKU

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H02M7/00

CPC classification number: H01L23/49562 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49513 ,  H01L24/48 ,  H01L23/3142 ,  H01L21/565 ,  H01L23/4952 ,  H01L23/49582 ,  H02M7/003 ,  H01L24/83 ,  H01L2224/48247 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L2924/30101 ,  H01L2924/13091 ,  H01L2224/83862

Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.