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公开(公告)号：US10778366B2
公开(公告)日：2020-09-15
申请号：US15940026
申请日：2018-03-29
Applicant: QUALCOMM Incorporated
Inventor： Vincent Loncke , Raghunath Kalavai , Yi Cao , Thomas Richardson , Joseph Binamira Soriaga , Shrinivas Kudekar
Abstract: Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.
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Patent Agency Ranking
公开(公告)号：US20180294917A1
公开(公告)日：2018-10-11
申请号：US15940026
申请日：2018-03-29
Applicant: QUALCOMM Incorporated
Inventor： Vincent Loncke , Raghunath Kalavai , Yi Cao , Thomas Richardson , Joseph Binamira Soriaga , Shrinivas Kudekar
IPC: H04L1/00
Abstract: Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.
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公开(公告)号：US10778371B2
公开(公告)日：2020-09-15
申请号：US15712845
申请日：2017-09-22
Applicant: QUALCOMM Incorporated
Inventor： Vincent Loncke , Girish Varatkar , Thomas Joseph Richardson , Yi Cao
Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.
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公开(公告)号：US20160216723A1
公开(公告)日：2016-07-28
申请号：US14606753
申请日：2015-01-27
Applicant: QUALCOMM Incorporated
Inventor： Zhengming Fu , James Thomas Doyle , Nazanin Darbanian , Shree Krishna Pandey , Yi Cao
IPC: G05F3/08
CPC classification number: G05F3/08 , G05F1/575 , H02M3/158 , H02M3/1582 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
Abstract translation: 诸如移动电话等复杂设备的片上系统芯片（SoC）集成电路的运行模式变化会导致电流需求的尖峰，从而导致电压下降，从而破坏了SoC的运行。 混合并联电源并联电容耦合开关电源和低压差稳压器，以提供高效率和快速的响应时间。 低压差稳压器可以包括驱动耦合电容器的AB类运算跨导放大器。 开关电源和低压差稳压器可以将其输出调节为稍微不同的电压电平。 这可以允许开关电源供应大部分SoC的当前需求。
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公开(公告)号：US10312937B2
公开(公告)日：2019-06-04
申请号：US15619168
申请日：2017-06-09
Applicant: QUALCOMM Incorporated
Inventor： Vincent Loncke , Yi Cao , Girish Varatkar
Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.
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公开(公告)号：US09891646B2
公开(公告)日：2018-02-13
申请号：US14606753
申请日：2015-01-27
Applicant: QUALCOMM Incorporated
Inventor： Zhengming Fu , James Thomas Doyle , Nazanin Darbanian , Shree Krishna Pandey , Yi Cao
CPC classification number: G05F3/08 , G05F1/575 , H02M3/158 , H02M3/1582 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
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