-
公开(公告)号：US20170371675A1
公开(公告)日：2017-12-28
申请号：US15191266
申请日：2016-06-23
Applicant: QUALCOMM Incorporated
Inventor： Weiwei Chen , Tushar Kumar
CPC classification number: G06F9/3869 , G06F9/30145 , G06F9/3867 , G06F9/3885
Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing an iteration synchronization construct (ISC) for a parallel pipeline. The apparatus may initialize a first instance of the ISC for a first stage iteration of a first parallel stage of the parallel pipeline and a second instance of the ISC for a second stage iteration of the first parallel stage of the parallel pipeline. The apparatus may determine whether an execution control value is specified for the first stage iteration, and add a first execution control edge to the parallel pipeline after determining that an execution control value is specified for the first stage iteration. The apparatus may determine whether execution of the first stage iteration is complete and send a ready signal from the first instance of the ISC to the second instance if the ISC after determining that execution of the first stage iteration completed.
-
公开(公告)号：US10114681B2
公开(公告)日：2018-10-30
申请号：US15085108
申请日：2016-03-30
Applicant: QUALCOMM Incorporated
Inventor： Dario Suarez Gracia , Gheorghe Cascaval , Han Zhao , Tushar Kumar , Aravind Natarajan , Arun Raman
Abstract: Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.
-
公开(公告)号：US10031697B2
公开(公告)日：2018-07-24
申请号：US15000667
申请日：2016-01-19
Applicant: QUALCOMM Incorporated
Inventor： Tushar Kumar , Aravind Natarajan , Dario Suarez Gracia
IPC: G06F9/54 , G06F3/06 , G06F12/1072 , G06F9/46 , G06F9/38
Abstract: Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.
-
公开(公告)号：US20170287185A1
公开(公告)日：2017-10-05
申请号：US15192051
申请日：2016-06-24
Applicant: QUALCOMM Incorporated
Inventor： Tushar Kumar , Wenhao Jia , Arun Raman , Hui Chao , Wenjia Ruan
CPC classification number: G06T11/60 , G06K9/36 , G06T3/4038 , G06T7/33 , G06T19/006 , H04N5/23222 , H04N5/23238
Abstract: Various embodiments may include methods executed by processors of computing devices for geometry based work execution prioritization. The processor may receive events, such as images. The processor may overlay a boundary shape on the event to identify discard regions of the event lying outside the boundary shape. The processor may identify work regions of the events lying within the working boundary shape. The devices may determine a cancellation likelihood for each of the identified work regions of the events. The processor may assign a trimming weight to each of the identified work regions based on the determined cancellation likelihoods. The processor may then add each of the identified work regions as a work item to an execution work list in an order based on the assigned trimming weights. The work items may be processed in order of trimming weight priority.
-
公开(公告)号：US10977092B2
公开(公告)日：2021-04-13
申请号：US14884979
申请日：2015-10-16
Applicant: QUALCOMM Incorporated
Inventor： Arun Raman , Tushar Kumar
Abstract: Embodiments include computing devices, apparatus, and methods implemented by a computing device for task scheduling in the presence of task conflict edges on a computing device. The computing device may determine whether a first task and a second task are related by a task conflict edge. In response to determining that the first task and the second task are related by the task conflict edge, the computing device may determine whether the second task acquires a resource required for execution of the first task and the second task. In response to determining that the second task fails to acquire the resource, the computing device may assign a dynamic task dependency edge from the first task to the second task.
-
Patent Agency Ranking
公开(公告)号：US10296074B2
公开(公告)日：2019-05-21
申请号：US15417605
申请日：2017-01-27
Applicant: QUALCOMM Incorporated
Inventor： Wenjia Ruan , Han Zhao , Tushar Kumar
IPC: G06F9/50 , G06F1/329 , G06F1/28 , G06F1/3228 , G06F9/48
Abstract: Various embodiments provide methods, devices, and non-transitory processor-readable storage media enabling joint goals, such as joint power and performance goals, to be realized on a per heterogeneous processing device basis for heterogeneous parallel computing constructs. Various embodiments may enable assignments of power states for heterogeneous processing devices on a per heterogeneous processing device basis to satisfy an overall goal on the heterogeneous processing construct. Various embodiments may enable dynamic adjustment of power states for heterogeneous processing devices on a per heterogeneous processing device basis.
-
公开(公告)号：US20170289445A1
公开(公告)日：2017-10-05
申请号：US15192102
申请日：2016-06-24
Applicant: QUALCOMM Incorporated
Inventor： Tushar Kumar , Wenhao Jia , Arun Raman , Hui Chao , Wenjia Ruan
IPC: H04N5/232
CPC classification number: G06T11/60 , G06K9/36 , G06T3/4038 , G06T7/33 , G06T19/006 , H04N5/23222 , H04N5/23238
Abstract: Various embodiments may include methods executed by processors of computing devices for geometry based work execution prioritization. The processor may receive events, such as images. The processor may overlay a boundary shape on the event to identify discard regions of the event lying outside the boundary shape. The processor may identify work regions of the events lying within the working boundary shape. The devices may determine a cancellation likelihood for each of the identified work regions of the events. The processor may assign a trimming weight to each of the identified work regions based on the determined cancellation likelihoods. The processor may then add each of the identified work regions as a work item to an execution work list in an order based on the assigned trimming weights. The work items may be processed in order of trimming weight priority.
-
公开(公告)号：US20170109217A1
公开(公告)日：2017-04-20
申请号：US14884979
申请日：2015-10-16
Applicant: QUALCOMM Incorporated
Inventor： Arun Raman , Tushar Kumar
CPC classification number: G06F9/524 , G06F9/5027 , G06F9/52
Abstract: Embodiments include computing devices, apparatus, and methods implemented by a computing device for task scheduling in the presence of task conflict edges on a computing device. The computing device may determine whether a first task and a second task are related by a task conflict edge. In response to determining that the first task and the second task are related by the task conflict edge, the computing device may determine whether the second task acquires a resource required for execution of the first task and the second task. In response to determining that the second task fails to acquire the resource, the computing device may assign a dynamic task dependency edge from the first task to the second task.
-
公开(公告)号：US10198838B2
公开(公告)日：2019-02-05
申请号：US15192102
申请日：2016-06-24
Applicant: QUALCOMM Incorporated
Inventor： Tushar Kumar , Wenhao Jia , Arun Raman , Hui Chao , Wenjia Ruan
Abstract: Various embodiments may include methods executed by processors of computing devices for geometry based work execution prioritization. The processor may receive events, such as images. The processor may overlay a boundary shape on the event to identify discard regions of the event lying outside the boundary shape. The processor may identify work regions of the events lying within the working boundary shape. The devices may determine a cancellation likelihood for each of the identified work regions of the events. The processor may assign a trimming weight to each of the identified work regions based on the determined cancellation likelihoods. The processor may then add each of the identified work regions as a work item to an execution work list in an order based on the assigned trimming weights. The work items may be processed in order of trimming weight priority.
-
公开(公告)号：US20180144521A1
公开(公告)日：2018-05-24
申请号：US15358515
申请日：2016-11-22
Applicant: QUALCOMM Incorporated
Inventor： Hui Chao , Tushar Kumar , Wenjia Ruan , Arun Raman
CPC classification number: G06T11/60 , G06T1/20 , G06T5/50 , G06T2207/10004
Abstract: Various embodiments may include methods executed by processors of computing devices for geometry based work execution prioritization of irregular shapes on a computing device. Various embodiments may include calculating cost functions for an irregularly shaped work region detected by the computing device. The processor may map the irregularly shaped work region to a geometrically-bounded first work region within an N-dimensional space. The processor may then assess the efficacy of implementing modification strategies such as merging work regions or splitting a large work region into sections. Two or more smaller work regions may be merged to create a larger work region that may be more easily processed by a processing unit. Similarly, large shapes may be split into multiple smaller regularly shaped work regions that may be processed by different processors.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.017 seconds)
