公开(公告)号：US20170371675A1

公开(公告)日：2017-12-28

申请号：US15191266

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Weiwei Chen ,  Tushar Kumar

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3869 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3885

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing an iteration synchronization construct (ISC) for a parallel pipeline. The apparatus may initialize a first instance of the ISC for a first stage iteration of a first parallel stage of the parallel pipeline and a second instance of the ISC for a second stage iteration of the first parallel stage of the parallel pipeline. The apparatus may determine whether an execution control value is specified for the first stage iteration, and add a first execution control edge to the parallel pipeline after determining that an execution control value is specified for the first stage iteration. The apparatus may determine whether execution of the first stage iteration is complete and send a ready signal from the first instance of the ISC to the second instance if the ISC after determining that execution of the first stage iteration completed.