公开(公告)号：US20190385948A1

公开(公告)日：2019-12-19

申请号：US16557728

申请日：2019-08-30

Applicant: QUALCOMM Incorporated

Inventor： Tin Tin WEE ,  Trilochan SAHOO ,  Sunil SUKUMARAPILLAI ,  Arun Kumar Kodigenahalli VENKATESWAR

IPC: H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088

Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first contact formed over a second portion of the one or more fins, wherein the first contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first contact to the first metal line, and a second via connecting the first contact to the second metal line, wherein the second via is placed on the extended portion of the first contact.

公开(公告)号：US20190304905A1

公开(公告)日：2019-10-03

申请号：US15992473

申请日：2018-05-30

Applicant: QUALCOMM Incorporated

Inventor： Tin Tin WEE ,  Alvin Leng Sun LOKE ,  Jacob SCHNEIDER

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L27/06

Abstract: Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias.

公开(公告)号：US20190067189A1

公开(公告)日：2019-02-28

申请号：US16159042

申请日：2018-10-12

Applicant: QUALCOMM Incorporated

Inventor： Tin Tin WEE ,  Trilochan SAHOO ,  Sunil SUKUMARAPILLAI ,  Arun Kumar Kodigenahalli VENKATESWAR

IPC: H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/785

Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.