Synchronization mechanism for image capture and processing systems

    公开(公告)号:US11283994B2

    公开(公告)日:2022-03-22

    申请号:US17109009

    申请日:2020-12-01

    Abstract: Techniques and systems are provided for processing image data. For example, an image signal processor can obtain (e.g., from a host processor) a first setting change indicator value indicating a change in parameter settings of the image signal processor. The image signal processor can obtain an image frame from an image sensor, and can determine a second setting change indicator value from the image frame. The second setting change indicator value can be provided to the image sensor from the host processor. The second setting change indicator value indicates a change in parameter settings of the image sensor. The image signal processor can compare the first setting change indicator value to the second setting change indicator value, and can determine whether to process the image frame or to drop the image frame based on comparing the first setting change indicator value to the second setting change indicator value.

    Image signal processor resource management

    公开(公告)号:US11438502B2

    公开(公告)日:2022-09-06

    申请号:US15931770

    申请日:2020-05-14

    Abstract: Aspects relate to an image signal processor that processes frames at changing frame rates. An example method includes receiving, by an image signal processor, a first sequence of image frames from an image sensor at a first frame rate, processing each image frame of the first sequence of image frames at the first frame rate, and receiving from the image sensor an indication of a frame rate change from the first frame rate to a second frame rate. The method also includes configuring one or more filters of the image signal processor to process image frames from the image sensor in response to receiving the indication of the frame rate change from the image sensor, receiving a second sequence of image frames from the image sensor at the second frame rate, and processing each image frame of the second sequence of image frames at the second frame rate.

    MULTI-CONTEXT DYNAMIC LINE BUFFER MANAGEMENT FOR IMAGE PROCESSING

    公开(公告)号:US20250056137A1

    公开(公告)日:2025-02-13

    申请号:US18448440

    申请日:2023-08-11

    Abstract: A system comprises an image signal processor (ISP). The ISP is a discrete hardware unit and includes a line buffer, a memory controller, and one or more image processors. The memory controller is configured to allocate blocks within the line buffer to a plurality of contexts, and for each of the contexts: receive one or more lines of image data associated with a respective context and store the one or more lines of the image data associated with the context in a respective block allocated to the respective context. The one or more image processors of the ISP are configured to, for each respective context of the plurality of contexts, process the one or more lines of the image data associated with the respective context that are stored in the line buffer.

    IMAGE FRAME PROCESSING FROM MULTIPLE IMAGE SENSORS

    公开(公告)号:US20220094829A1

    公开(公告)日:2022-03-24

    申请号:US17031261

    申请日:2020-09-24

    Abstract: Aspects relate to an image signal processor that processes frames from different image sensors. An example device includes a memory and an image signal processor coupled to the memory. The image signal processor is configured to provide a first trigger to a first image sensor (the first image sensor being coupled to the image signal processor), receive a first frame from the first image sensor at a first time in response to the first trigger being received by the first image sensor, process the first frame, provide a second trigger to the second image sensor (the second image sensor being coupled to the image signal processor), receive a second frame from the second image sensor at a second time in response to the second trigger being received by the second image sensor (with the second time subsequent to the first time), and process the second frame.

    IMAGE SIGNAL PROCESSOR SUPPORTING MULTIPLE SECURITY DOMAINS ON A SHARED PHYSICAL LINK

    公开(公告)号:US20240205539A1

    公开(公告)日:2024-06-20

    申请号:US18069100

    申请日:2022-12-20

    CPC classification number: H04N23/665 H04N23/45 H04W12/086

    Abstract: This disclosure provides systems, methods, and devices for wireless communication that support improved routing of image sensors that share a PHY within different secure domains. In a first aspect, a device may receive a packet from an image sensor along a physical data connection. The device may determine a virtual channel associated with the packet and may determining a secure domain for the packet based on the virtual channel. The first secure domain may be selected from a plurality of secure domains accessible via the physical data connection, such as based on a mapping maintained by the device. The device may then route the packet within the first secure domain such that further processing and storage of the packet occurs within the first secure domain, such as within a context base associated with the first secure domain. Other aspects and features are also claimed and described.

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