公开(公告)号：US20250056137A1

公开(公告)日：2025-02-13

申请号：US18448440

申请日：2023-08-11

Applicant: QUALCOMM Incorporated

Inventor： Vinod Kumar Nahval ,  Mei Yang ,  Srivaishnavi Sree Krishnan ,  Rohan Desai

IPC: H04N25/75 ,  H04N25/42 ,  H04N25/77

Abstract: A system comprises an image signal processor (ISP). The ISP is a discrete hardware unit and includes a line buffer, a memory controller, and one or more image processors. The memory controller is configured to allocate blocks within the line buffer to a plurality of contexts, and for each of the contexts: receive one or more lines of image data associated with a respective context and store the one or more lines of the image data associated with the context in a respective block allocated to the respective context. The one or more image processors of the ISP are configured to, for each respective context of the plurality of contexts, process the one or more lines of the image data associated with the respective context that are stored in the line buffer.