公开(公告)号：US09830134B2

公开(公告)日：2017-11-28

申请号：US14958572

申请日：2015-12-03

Applicant: QUALCOMM Incorporated

Inventor： Lee Howes

IPC: G06F9/45

CPC classification number: G06F8/41 ,  G06F8/443 ,  G06F8/447 ,  G06F8/452 ,  G06F8/456

Abstract: Examples are described for a device to receive intermediate code that was generated from compiling source code of an application. The intermediate code includes information generated from the compiling that identifies a hierarchical structure of lower level sub-routines in higher level sub-routines, and the lower level sub-routines are defined in the source code of the application to execute more frequently than the higher level sub-routines that identify the lower level sub-routines. The device is configured to compile the intermediate code to generate object code based on the information that identifies lower level sub-routines in higher level sub-routines, and store the object code.

公开(公告)号：US09779469B2

公开(公告)日：2017-10-03

申请号：US14828215

申请日：2015-08-17

Applicant: QUALCOMM Incorporated

Inventor： Lee Howes ,  Maxim Kazakov

IPC: G06T1/60 ,  G06F3/06 ,  G06F9/45 ,  G06T1/20 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06T1/20 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0683 ,  G06F8/441 ,  G06F9/30127 ,  G06F9/30138 ,  G06F9/462 ,  G06T1/60

Abstract: Techniques are described for copying data only from a subset of memory locations allocated to a set of instructions to free memory locations for higher priority instructions to execute. Data from a dynamic portion of one or more general purpose registers (GPRs) allocated to the set of instructions may be copied and stored to another memory unit while data from a static portion of the one or more GPRs allocated to the set of instructions may not be copied and stored to another memory unit.

公开(公告)号：US20160364216A1

公开(公告)日：2016-12-15

申请号：US14958572

申请日：2015-12-03

Applicant: QUALCOMM Incorporated

Inventor： Lee Howes

IPC: G06F9/45

CPC classification number: G06F8/41 ,  G06F8/443 ,  G06F8/447 ,  G06F8/452 ,  G06F8/456

Abstract: Examples are described for a device to receive intermediate code that was generated from compiling source code of an application. The intermediate code includes information generated from the compiling that identifies a hierarchical structure of lower level sub-routines in higher level sub-routines, and the lower level sub-routines are defined in the source code of the application to execute more frequently than the higher level sub-routines that identify the lower level sub-routines. The device is configured to compile the intermediate code to generate object code based on the information that identifies lower level sub-routines in higher level sub-routines, and store the object code.

Abstract translation: 描述了用于接收从编译应用程序的源代码生成的中间代码的设备的示例。 中间代码包括从编译中生成的信息，其识别较高级子例程中较低级子例程的层次结构，并且较低级子例程在应用的源代码中被定义为比较高级的子例程更频繁执行 标识较低级子例程的级别子例程。 该设备被配置为基于识别较高级子例程中的较低级子例程的信息来编译中间代码以生成目标代码，并存储目标代码。

公开(公告)号：US09720691B2

公开(公告)日：2017-08-01

申请号：US14863030

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Lee Howes

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F9/455

CPC classification number: G06F9/30036 ,  G06F8/4432 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/45525 ,  G06F15/8007 ,  G06F15/8053 ,  Y02D10/41

Abstract: In an example, a method for speculative scalarization may include receiving, by a first processor, vector code. The method may include determining, during compilation of the vector code, whether at least one instruction of the plurality of instructions is a speculatively uniform instruction. The method may include generating, during complication of the vector code, uniformity detection code for the at least one speculatively uniform instruction. The uniformity detection code, when executed, may be configured to determine whether the at least one speculatively uniform instruction is uniform during runtime. The method may include generating, during complication of the vector code, scalar code by scalarizing the at least one speculatively uniform instruction. The scalar code may be configured to be compiled for execution by the first processor, a scalar processor, a scalar processing unit of the vector processor, or a vector pipeline of the vector processor.

公开(公告)号：US20170083323A1

公开(公告)日：2017-03-23

申请号：US14863030

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Lee Howes

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F8/4432 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/45525 ,  G06F15/8007 ,  G06F15/8053 ,  Y02D10/41

Abstract: In an example, a method for speculative scalarization may include receiving, by a first processor, vector code. The method may include determining, during compilation of the vector code, whether at least one instruction of the plurality of instructions is a speculatively uniform instruction. The method may include generating, during complication of the vector code, uniformity detection code for the at least one speculatively uniform instruction. The uniformity detection code, when executed, may be configured to determine whether the at least one speculatively uniform instruction is uniform during runtime. The method may include generating, during complication of the vector code, scalar code by scalarizing the at least one speculatively uniform instruction. The scalar code may be configured to be compiled for execution by the first processor, a scalar processor, a scalar processing unit of the vector processor, or a vector pipeline of the vector processor.

公开(公告)号：US20170053374A1

公开(公告)日：2017-02-23

申请号：US14828215

申请日：2015-08-17

Applicant: QUALCOMM Incorporated

Inventor： Lee Howes ,  Maxim Kazakov

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/06

CPC classification number: G06T1/20 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0683 ,  G06F8/441 ,  G06F9/30127 ,  G06F9/30138 ,  G06F9/462 ,  G06T1/60

Abstract: Techniques are described for copying data only from a subset of memory locations allocated to a set of instructions to free memory locations for higher priority instructions to execute. Data from a dynamic portion of one or more general purpose registers (GPRs) allocated to the set of instructions may be copied and stored to another memory unit while data from a static portion of the one or more GPRs allocated to the set of instructions may not be copied and stored to another memory unit.

Abstract translation: 描述了仅将分配给一组指令的存储器位置的子集的数据复制到用于执行更高优先级指令的空闲存储器位置的技术。 分配给该组指令的一个或多个通用寄存器（GPR）的动态部分的数据可以被复制并存储到另一存储器单元，而来自分配给该组指令的一个或多个GPR的静态部分的数据可能不 复制并存储到另一个存储单元。