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    WIRELESS TRANSMITTER WITH BIAS CONTROL
    2.
    发明公开
    WIRELESS TRANSMITTER WITH BIAS CONTROL 审中-公开

    公开(公告)号：US20240283473A1

    公开(公告)日：2024-08-22

    申请号：US18521108

    申请日：2023-11-28

    Applicant: QUALCOMM Incorporated

    Inventor： Ibrahim Ramez CHAMAS ,  Hayg-Taniel DABAG ,  Asad Ali NAWAZ ,  Huan WANG ,  Waqas AHMAD ,  Bhushan Shanti ASURI

    IPC: H04B1/04 ,  H03F3/24 ,  H04B1/30

    CPC classification number: H04B1/0475 ,  H03F3/24 ,  H04B1/30

    Abstract: Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to wireless transmitters. One example apparatus generally includes: an in-phase direct-current (DC) level shifter; a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit being coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter; and a quadrature mixer having an input coupled to an output of the quadrature V2I converter.

    CLOCK SPUR REDUCTION VIA PHASE-CONTROLLED REPLICA PATH
    5.
    发明申请
    CLOCK SPUR REDUCTION VIA PHASE-CONTROLLED REPLICA PATH 有权

    公开(公告)号：US20250062754A1

    公开(公告)日：2025-02-20

    申请号：US18449552

    申请日：2023-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Shahin MEHDIZAD TALEIE ,  Dongwon SEO ,  Bhushan Shanti ASURI ,  Ibrahim Ramez CHAMAS ,  Huan WANG ,  Zhiheng WANG ,  Reza RODD

    IPC: H03K5/01 ,  H03K19/20

    Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

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