公开(公告)号：US20150287709A1

公开(公告)日：2015-10-08

申请号：US14247214

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： HariKrishna CHINTARLAPALLI REDDY ,  Son LE ,  Ohsang KWON ,  Vijayalakshmi RANGANNA

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/092

Abstract: A double patterned CMOS device includes a first set of stacked transistors, a second set of stacked transistors, and a set of transistors. The first set of stacked transistors includes first and second transistors. The first transistor has a first transistor active region and the second transistor has a second transistor active region. The second set of stacked transistors is adjacent the first set of stacked transistors. The second set of stacked transistors includes third and fourth transistors. The third transistor has a third transistor active region and the fourth transistor has a fourth transistor active region. The set of transistors is adjacent the first set of stacked transistors. The set of transistors includes a fifth transistor. The fifth transistor has a fifth transistor active region. The first, second, third, and fourth transistor active regions satisfy certain distance relationships from each other.

Abstract translation: 双重图案化CMOS器件包括第一组堆叠晶体管，第二组堆叠晶体管和一组晶体管。 第一组堆叠晶体管包括第一和第二晶体管。 第一晶体管具有第一晶体管有源区，而第二晶体管具有第二晶体管有源区。 第二组堆叠晶体管与第一组堆叠晶体管相邻。 第二组堆叠晶体管包括第三和第四晶体管。 第三晶体管具有第三晶体管有源区，第四晶体管具有第四晶体管有源区。 该组晶体管与第一组堆叠晶体管相邻。 晶体管组包括第五晶体管。 第五晶体管具有第五晶体管有源区。 第一，第二，第三和第四晶体管有源区域彼此满足一定的距离关系。

公开(公告)号：US20150255461A1

公开(公告)日：2015-09-10

申请号：US14458228

申请日：2014-08-12

Applicant: QUALCOMM Incorporated

Inventor： HariKrishna CHINTARLAPALLI REDDY ,  Jay Madhukar SHAH ,  Ananth Haliyur GOPALAKRISHNA

IPC: H01L27/092 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L27/0886

Abstract: A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.

Abstract translation: MOS器件包括具有第一晶体管源极，漏极，栅极和鳍片组的第一FinFET，并且包括具有第二晶体管源极，漏极，栅极和鳍片组的第二FinFET。 MOS器件进一步包括栅极互连线性地延伸以形成并将第一和第二晶体管栅极连接在一起。 所述MOS器件还包括在所述栅极互连的第一侧上的第一互连，所述第一互连将所述第一晶体管漏极处的所述第一晶体管鳍片集合在所述第二晶体管源处的所述第二晶体管鳍片组， 在第一晶体管源处将第一晶体管鳍片集合在一起的栅极互连以及栅极互连的第二侧上的第三互连，其将第二晶体管漏极的第二晶体管鳍片组连接在一起。