DOUBLE PATTERNED STACKING TECHNIQUE
    1.
    发明申请
    DOUBLE PATTERNED STACKING TECHNIQUE 审中-公开
    双重图案堆叠技术

    公开(公告)号:US20150287709A1

    公开(公告)日:2015-10-08

    申请号:US14247214

    申请日:2014-04-07

    CPC classification number: H01L27/0207 H01L27/092

    Abstract: A double patterned CMOS device includes a first set of stacked transistors, a second set of stacked transistors, and a set of transistors. The first set of stacked transistors includes first and second transistors. The first transistor has a first transistor active region and the second transistor has a second transistor active region. The second set of stacked transistors is adjacent the first set of stacked transistors. The second set of stacked transistors includes third and fourth transistors. The third transistor has a third transistor active region and the fourth transistor has a fourth transistor active region. The set of transistors is adjacent the first set of stacked transistors. The set of transistors includes a fifth transistor. The fifth transistor has a fifth transistor active region. The first, second, third, and fourth transistor active regions satisfy certain distance relationships from each other.

    Abstract translation: 双重图案化CMOS器件包括第一组堆叠晶体管,第二组堆叠晶体管和一组晶体管。 第一组堆叠晶体管包括第一和第二晶体管。 第一晶体管具有第一晶体管有源区,而第二晶体管具有第二晶体管有源区。 第二组堆叠晶体管与第一组堆叠晶体管相邻。 第二组堆叠晶体管包括第三和第四晶体管。 第三晶体管具有第三晶体管有源区,第四晶体管具有第四晶体管有源区。 该组晶体管与第一组堆叠晶体管相邻。 晶体管组包括第五晶体管。 第五晶体管具有第五晶体管有源区。 第一,第二,第三和第四晶体管有源区域彼此满足一定的距离关系。

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