公开(公告)号：US20190087345A1

公开(公告)日：2019-03-21

申请号：US15709884

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Farrukh HIJAZ ,  George PATSILARAS

IPC: G06F12/0897 ,  G06F12/0891 ,  G06F12/0877

Abstract: Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.

公开(公告)号：US20150370707A1

公开(公告)日：2015-12-24

申请号：US14313166

申请日：2014-06-24

Applicant: QUALCOMM Incorporated

Inventor： George PATSILARAS ,  Bohuslav RYCHLIK ,  Anwar ROHILLAH

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0811 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0815 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0848 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1056 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Systems and methods pertain to a multiprocessor system comprising disunited cache structures. A first private-information cache is coupled to a first processor of the multiprocessor system. The first private-information cache is configured to store information that is private to the first processor. A first shared-information cache which is disunited from the first private-information cache is also coupled to the first processor. The first shared-information cache is configured to store information that is shared/shareable between the first processor and one or more other processors of the multiprocessor system.

Abstract translation: 系统和方法涉及包含不完整缓存结构的多处理器系统。 第一私人信息缓存耦合到多处理器系统的第一处理器。 第一私人信息缓存被配置为存储对第一处理器是私有的信息。 与第一专用信息高速缓存分离的第一共享信息高速缓存也耦合到第一处理器。 第一共享信息缓存被配置为存储在第一处理器和多处理器系统的一个或多个其他处理器之间共享/共享的信息。

公开(公告)号：US20150293847A1

公开(公告)日：2015-10-15

申请号：US14251628

申请日：2014-04-13

Applicant: QUALCOMM Incorporated

Inventor： George PATSILARAS ,  Moinul H. KHAN ,  Pankaj CHAURASIA ,  Bohuslav RYCHLIK ,  Feng WANG ,  Anwar Q. ROHILLAH ,  Subbarao PALACHARLA

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F1/3275 ,  G06F12/0808 ,  G06F12/0868 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14

Abstract: Ephemeral data stored in a cache is read when needed but is not written to system memory so as to save power and bandwidth. In an embodiment, a no-writeback bit associated with the ephemeral data is set in response to a read-no-writeback instruction. Data in a cache line for which its no-writeback bit has been set is not written back into system memory. Accordingly, when evicting cache lines, if a cache line has a no-writeback bit set, then the data in that cache line is discarded without being written back to system memory.

Abstract translation: 存储在缓存中的短暂数据在需要时被读取，但不会写入系统内存，以节省功耗和带宽。 在一个实施例中，响应于无写回指令来设置与短暂数据相关联的无回写位。 已设置其无回写位的高速缓存行中的数据不会写入系统内存。 因此，当驱逐高速缓存行时，如果高速缓存行具有无回写位设置，则该高速缓存行中的数据被丢弃而不被写回系统存储器。

公开(公告)号：US20230421998A1

公开(公告)日：2023-12-28

申请号：US18460149

申请日：2023-09-01

Applicant: QUALCOMM Incorporated

Inventor： Mohit Hari BHAVE ,  Aravind BHASKARA ,  Shengqi YANG ,  Aswin SAMPATH KUMARAN ,  Ling Feng HUANG ,  Jyotirmoy DAS ,  George PATSILARAS

IPC: H04W4/029 ,  G01S5/08 ,  G01S5/02

CPC classification number: H04W4/029 ,  G01S5/08 ,  G01S5/0218

Abstract: A device includes a memory configured to store video data. The device also includes a video decoder coupled to the memory and to a cache. The video decoder is configured to decode an input frame of the video data to generate a first video frame and includes an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output.

公开(公告)号：US20230031310A1

公开(公告)日：2023-02-02

申请号：US17390215

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： ENGIN IPEK ,  Bohuslav RYCHLIK ,  George PATSILARAS ,  Prajakt KULKARNI ,  Can HANKENDI ,  Fahad ALI ,  Jeffrey GEMAR ,  Matthew SEVERSON

IPC: G06F13/16

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

公开(公告)号：US20210049099A1

公开(公告)日：2021-02-18

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： ANDREW EDMUND TURNER ,  George PATSILARAS ,  Bohuslav RYCHLIK ,  Wesley James HOLLAND ,  Jeffrey SHABEL ,  Simon Peter William BOOTH

IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US20240386980A1

公开(公告)日：2024-11-21

申请号：US18522098

申请日：2023-11-28

Applicant: QUALCOMM Incorporated

Inventor： Simon Peter William BOOTH ,  Subbarao PALACHARLA ,  George PATSILARAS ,  Hiral NANDU ,  Girish BHAT ,  Yen-Kuan WU

IPC: G11C29/12

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain an indication of a data write for data associated with data processing. The apparatus may write, based on the indication, the data associated with the data processing to a memory address. The apparatus may receive a read request for the data including the memory address, where the read request is associated with a read with invalidate process. The apparatus may retrieve, based on the read request, the data from at least one of a first cache or at least one second memory, where the retrieval of the data is based on a timing of the indication of the data write. The apparatus may output the retrieved data from at least one of the first cache or the at least one second memory.

公开(公告)号：US20210200679A1

公开(公告)日：2021-07-01

申请号：US17204534

申请日：2021-03-17

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund TURNER ,  George PATSILARAS ,  Bohuslav RYCHLIK ,  Wesley James HOLLAND ,  Jeffrey SHABEL ,  Simon Peter William BOOTH

IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072 ,  G06F12/0868

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US20160350152A1

公开(公告)日：2016-12-01

申请号：US14866012

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GADELRAB ,  Christopher Edward KOOB ,  Simon BOOTH ,  Aris BALATSOS ,  Johnny Jone Wai KUAN ,  Myil RAMKUMAR ,  Bhupinder Singh PABLA ,  Sean David SWEENEY ,  George PATSILARAS

IPC: G06F9/48 ,  G06F11/07

CPC classification number: G06F9/4818 ,  G06F9/46 ,  G06F9/4887 ,  G06F11/0724 ,  G06F11/079 ,  G06F2209/506

Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

Abstract translation: 系统和方法涉及在包括两个或多个处理线程的多线程处理器中管理共享资源。 确定两个或更多个线程的危险水平，其中线程的危险等级基于线程由于不可用的共享资源而遇到期限的潜在故障。 还确定与两个或更多个线程相关联的优先级，其中对于不能达到期限的线程而言，优先级高于不能接受的线程，并且对于不满足截止期限的线程，优先级较低。 至少基于与两个或多个线程相关联的两个或多个线程的确定的危险等级和优先级，来调度两个或更多个线程。

公开(公告)号：US20160077973A1

公开(公告)日：2016-03-17

申请号：US14483902

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： George PATSILARAS ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0886 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

Abstract translation: 方面包括计算设备，系统和方法，用于使用高速缓存存储体扩展来实现用于压缩数据的高速缓存存储器访问请求。 在一方面，高速缓存存储体扩展可以包括确定高速缓冲存储器访问的压缩数据是否适合于单个高速缓存存储体。 响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以代替/恢复可以在数据期间清除的高速缓冲存储器访问请求的高速缓冲存储器的物理地址的存储体选择位 压缩。 高速缓冲存储器的物理空间中的高速缓存存储体扩展地址可以包括高速缓冲存储器访问请求的物理地址加上恢复的存储体选择位。 缓存存储体扩展地址可用于从压缩数据读取压缩数据或将压缩数据写入缓存存储器件。