公开(公告)号：US20190132513A1

公开(公告)日：2019-05-02

申请号：US15794673

申请日：2017-10-26

Applicant: QUALCOMM Incorporated

Inventor： Aravind BHASKARA ,  Wenbiao WANG ,  Tao SHEN ,  Mohit BHAVE ,  Nishant HARIHARAN ,  Jun LIU ,  Jeffrey Hao CHU ,  Scott CHENG

IPC: H04N5/232 ,  H04N5/907

Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

公开(公告)号：US20240276096A1

公开(公告)日：2024-08-15

申请号：US18165189

申请日：2023-02-06

Applicant: QUALCOMM Incorporated

Inventor： Aravind BHASKARA ,  Tauseef KAZI ,  Zhurang ZHAO ,  Rohan DESAI ,  Michael TIPTON ,  Joshua STUBBS ,  Kiran BHAGWAT ,  Pavan Kumar CHILAMKURTHI

IPC: H04N23/65 ,  H04N25/71

CPC classification number: H04N23/651 ,  H04N25/745

Abstract: Systems, methods, and computer-readable media are provided for camera dynamic voting to optimize fast sensor mode power. In some examples, a computing device can obtain, based on performing dynamic voting, a plurality of votes associated with a plurality of components sharing a power source. The computing device can determine a voting result based on the plurality of votes. The computing device can increase or decreasing a clock rate and a voltage for the power source based on the voting result to produce an updated clock rate and an updated voltage. The computing device can then apply the updated clock rate and the updated voltage to an image processor.

公开(公告)号：US20240201762A1

公开(公告)日：2024-06-20

申请号：US18082518

申请日：2022-12-15

Applicant: QUALCOMM Incorporated

Inventor： Aravind BHASKARA ,  Zhurang ZHAO ,  Kiran BHAGWAT ,  Michael TIPTON ,  Joshua STUBBS ,  Jyotirmoy DAS ,  Thomas TANG

IPC: G06F1/26 ,  G06F1/08

CPC classification number: G06F1/26 ,  G06F1/08

Abstract: Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.

公开(公告)号：US20230421998A1

公开(公告)日：2023-12-28

申请号：US18460149

申请日：2023-09-01

Applicant: QUALCOMM Incorporated

Inventor： Mohit Hari BHAVE ,  Aravind BHASKARA ,  Shengqi YANG ,  Aswin SAMPATH KUMARAN ,  Ling Feng HUANG ,  Jyotirmoy DAS ,  George PATSILARAS

IPC: H04W4/029 ,  G01S5/08 ,  G01S5/02

CPC classification number: H04W4/029 ,  G01S5/08 ,  G01S5/0218

Abstract: A device includes a memory configured to store video data. The device also includes a video decoder coupled to the memory and to a cache. The video decoder is configured to decode an input frame of the video data to generate a first video frame and includes an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output.