公开(公告)号：US11908537B2

公开(公告)日：2024-02-20

申请号：US18163146

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： David Li ,  Rahul Biradar ,  Biju Manakkam Veetil ,  Po-Hung Chen ,  Ayan Paul ,  Sung Son ,  Shivendra Kushwaha ,  Ravindra Reddy Chekkera ,  Derek Yang

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C5/025 ,  G11C7/06 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US11170845B1

公开(公告)日：2021-11-09

申请号：US16928658

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Derek Yang ,  Chulmin Jung ,  Changho Jung

IPC: G11C8/08 ,  G11C11/418

Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

公开(公告)号：US09941881B1

公开(公告)日：2018-04-10

申请号：US15467943

申请日：2017-03-23

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Derek Yang ,  Sei Seung Yoon

IPC: H03K19/20 ,  H03K19/003 ,  H03K19/0948

CPC classification number: H03K19/00323 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0948 ,  H03K19/20

Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

公开(公告)号：US11600307B2

公开(公告)日：2023-03-07

申请号：US17136616

申请日：2020-12-29

Applicant: QUALCOMM Incorporated

Inventor： David Li ,  Rahul Biradar ,  Biju Manakkam Veetil ,  Po-Hung Chen ,  Ayan Paul ,  Sung Son ,  Shivendra Kushwaha ,  Ravindra Reddy Chekkera ,  Derek Yang

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.