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    Power-density-based clock cell spacing
    2.
    发明授权
    Power-density-based clock cell spacing 有权

    公开(公告)号：US09824174B2

    公开(公告)日：2017-11-21

    申请号：US14852340

    申请日：2015-09-11

    Applicant: QUALCOMM Incorporated

    Inventor： Ankita Nayak ,  David Anthony Kidd ,  Paul Ivan Penzes

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/62

    Abstract: Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

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