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    LOGICAL TO PHYSICAL LOOKUP TABLE UPDATE IN A FLASH MEMORY SYSTEM
    1.
    发明申请
    LOGICAL TO PHYSICAL LOOKUP TABLE UPDATE IN A FLASH MEMORY SYSTEM 有权

    公开(公告)号：US20240370378A1

    公开(公告)日：2024-11-07

    申请号：US18310295

    申请日：2023-05-01

    Applicant: QUALCOMM Incorporated

    Inventor： Santhosh Reddy Akavaram ,  Sonali Jabreva ,  Prakhar Srivastava

    IPC: G06F12/1009

    Abstract: This disclosure provides systems, methods, and devices for memory systems that support updating a logical to physical (L2P) table of a host device in accordance with one or more updates to a corresponding L2P table of a memory system. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving an indication of an update to a first logical to physical (L2P) table stored on a first memory of a memory system and updating a second L2P table stored on a second memory of the host device in accordance with the update to the first L2P table. Other aspects and features are also claimed and described.

    Memory devices write buffer management
    2.
    发明授权
    Memory devices write buffer management 有权

    公开(公告)号：US12197775B2

    公开(公告)日：2025-01-14

    申请号：US18189141

    申请日：2023-03-23

    Applicant: QUALCOMM Incorporated

    Inventor： Santhosh Reddy Akavaram ,  Sonali Jabreva ,  Prakhar Srivastava ,  Surendra Paravada ,  Yogananda Rao Chillariga ,  Madhu Yashwanth Boenapalli

    IPC: G06F3/06

    Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

    System and method for updating memory tables
    4.
    发明授权
    System and method for updating memory tables 有权

    公开(公告)号：US12271303B2

    公开(公告)日：2025-04-08

    申请号：US18349206

    申请日：2023-07-10

    Applicant: QUALCOMM Incorporated

    Inventor： Manish Garg ,  Pratibind Kumar Jha ,  Prakhar Srivastava ,  Santhosh Reddy Akavaram

    IPC: G06F12/02

    Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

    Mechanism To Improve The Reliability Of Sideband In Chiplets
    5.
    发明申请
    Mechanism To Improve The Reliability Of Sideband In Chiplets 有权

    公开(公告)号：US20250086136A1

    公开(公告)日：2025-03-13

    申请号：US18466299

    申请日：2023-09-13

    Applicant: QUALCOMM Incorporated

    Inventor： Ravindranath DODDI ,  Umamaheshwaran V ,  Afreen HAIDER ,  Lekhya Pavani GODAVARTHI ,  Harinatha Reddy RAMIREDDY ,  James Lionel Panian ,  Ramacharan Sundararaman ,  Santhosh Reddy Akavaram

    IPC: G06F13/42 ,  G06F15/78

    Abstract: Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.

    Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe
    7.
    发明授权
    Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe 有权

    公开(公告)号：US12164448B2

    公开(公告)日：2024-12-10

    申请号：US17821399

    申请日：2022-08-22

    Applicant: QUALCOMM Incorporated

    Inventor： Ravindranath Doddi ,  Santhosh Reddy Akavaram ,  Prakhar Srivastava

    IPC: G06F13/00 ,  G06F13/16

    Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link state transition by a computing device. Embodiments may include comprising retrieving, by a PCIe controller, PCIe link configuration data from a memory for a PCIe link in a fast recovery low power state of a link training status and state machine (LTSSM), and re-initializing, by the PCIe controller, the PCIe link using the PCIe link configuration data retrieved from the memory. Embodiments may further include maintaining the PCIe link configuration data in the memory for the PCIe link in the fast recovery low power state of the LTSSM by providing auxiliary power to PCIe configuration registers for the PCIe controller.

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