公开(公告)号：US12153527B2

公开(公告)日：2024-11-26

申请号：US18081396

申请日：2022-12-14

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy Akavaram ,  Prakhar Srivastava ,  Rajendra Varma Pusapati ,  Ravindranath Doddi ,  Yogananda Rao Chillariga

IPC: G06F13/40 ,  G06F13/12

Abstract: Aspects relate to lane failure recovery for a data link having multiple lanes labeled in a contiguous sequence. In one aspect, a failure of a failed lane of the data link is detected. Working lanes of the data link are then detected. A set of contiguous working lanes of the data link are selected, and an operational link as including the selected set of contiguous working lanes is defined. A start address of the operational link is identified and stored in a configuration register. Data traffic is transmitted on the operational link.

公开(公告)号：US12019577B2

公开(公告)日：2024-06-25

申请号：US17960050

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Santhosh Reddy Akavaram ,  Ravindranath Doddi ,  Ravi Kumar Sepuri

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4031 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.

公开(公告)号：US12164448B2

公开(公告)日：2024-12-10

申请号：US17821399

申请日：2022-08-22

Applicant: QUALCOMM Incorporated

Inventor： Ravindranath Doddi ,  Santhosh Reddy Akavaram ,  Prakhar Srivastava

IPC: G06F13/00 ,  G06F13/16

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link state transition by a computing device. Embodiments may include comprising retrieving, by a PCIe controller, PCIe link configuration data from a memory for a PCIe link in a fast recovery low power state of a link training status and state machine (LTSSM), and re-initializing, by the PCIe controller, the PCIe link using the PCIe link configuration data retrieved from the memory. Embodiments may further include maintaining the PCIe link configuration data in the memory for the PCIe link in the fast recovery low power state of the LTSSM by providing auxiliary power to PCIe configuration registers for the PCIe controller.

公开(公告)号：US12079061B2

公开(公告)日：2024-09-03

申请号：US17959996

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Santhosh Reddy Akavaram ,  Ravindranath Doddi ,  Ravi Kumar Sepuri

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/42

CPC classification number: G06F1/3278 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

公开(公告)号：US20240264965A1

公开(公告)日：2024-08-08

申请号：US18165698

申请日：2023-02-07

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Santhosh Reddy Akavaram ,  Yogananda Rao Chillariga ,  Ravindranath Doddi ,  Ravi Kumar Sepuri

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F2213/0026

Abstract: This disclosure provides systems, methods, and devices for interconnecting components of an electronic device through a bus interface that supports dynamic link configuration for changing bandwidth requirements on a bus. In a first aspect, a method of communicating through a bus by a bus interface includes determining a transmit data rate and a receive data rate for a workload of the first device; transmitting a link configuration change request to a second device through the bus to reconfigure the link from a first link configuration to a second link configuration; and communicating over the bus based on the link configuration change. Other aspects and features are also claimed and described.

公开(公告)号：US11934335B2

公开(公告)日：2024-03-19

申请号：US17715792

申请日：2022-04-07

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Ravindranath Doddi ,  Santhosh Reddy Akavaram

IPC: G06F13/42 ,  G06F1/08 ,  G06F1/3234 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F1/08 ,  G06F1/3253 ,  G06F13/4072

Abstract: Aspects relate to power management for a peripheral component interconnect. Transmit traffic activity may be monitored for a peripheral component interconnect express (PCIe) link. Receive traffic activity may also be monitored for the link A first power of transmit lines of the link is managed as a transmit group in accordance with the transmit traffic activity. A second power of the receive lines of the link are managed as a receive group in accordance with the receive traffic activity. The first power of the transmit lines is managed independently of the second power of the receive lines.