公开(公告)号：US12019577B2

公开(公告)日：2024-06-25

申请号：US17960050

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Santhosh Reddy Akavaram ,  Ravindranath Doddi ,  Ravi Kumar Sepuri

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4031 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.

公开(公告)号：US12079061B2

公开(公告)日：2024-09-03

申请号：US17959996

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Santhosh Reddy Akavaram ,  Ravindranath Doddi ,  Ravi Kumar Sepuri

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/42

CPC classification number: G06F1/3278 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

公开(公告)号：US20240264965A1

公开(公告)日：2024-08-08

申请号：US18165698

申请日：2023-02-07

Applicant: QUALCOMM Incorporated

Inventor： Prakhar Srivastava ,  Santhosh Reddy Akavaram ,  Yogananda Rao Chillariga ,  Ravindranath Doddi ,  Ravi Kumar Sepuri

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F2213/0026

Abstract: This disclosure provides systems, methods, and devices for interconnecting components of an electronic device through a bus interface that supports dynamic link configuration for changing bandwidth requirements on a bus. In a first aspect, a method of communicating through a bus by a bus interface includes determining a transmit data rate and a receive data rate for a workload of the first device; transmitting a link configuration change request to a second device through the bus to reconfigure the link from a first link configuration to a second link configuration; and communicating over the bus based on the link configuration change. Other aspects and features are also claimed and described.