Invention Application
- Patent Title: Mechanism To Improve The Reliability Of Sideband In Chiplets
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Application No.: US18466299Application Date: 2023-09-13
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Publication No.: US20250086136A1Publication Date: 2025-03-13
- Inventor: Ravindranath DODDI , Umamaheshwaran V , Afreen HAIDER , Lekhya Pavani GODAVARTHI , Harinatha Reddy RAMIREDDY , James Lionel Panian , Ramacharan Sundararaman , Santhosh Reddy Akavaram
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F15/78

Abstract:
Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.
Information query