公开(公告)号：US10109619B2

公开(公告)日：2018-10-23

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Mohammed Yousuff Shariff ,  Parissa Najdesamii ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/535 ,  H01L27/088 ,  G06F17/50 ,  H01L21/8238

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

公开(公告)号：US20150200667A1

公开(公告)日：2015-07-16

申请号：US14155734

申请日：2014-01-15

Applicant: QUALCOMM Incorporated

Inventor： Shiva Ram Chandrasekaran ,  Chandrasekhar Reddy Singasani ,  Joey Dacanay ,  Mamta Bansal ,  Arman Ohanian ,  Satish Raj ,  Kiran Srinivasa Sastry ,  Abhirami Senthilkumaran ,  Tarek Zghal ,  Parissa Najdesamii ,  Sunil Kumar

IPC: H03K19/00 ,  G06F1/32

CPC classification number: H03K19/0008 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods.

Abstract translation: 提供了用于降低与集成电路或系统的各种核心模块相关联的接口和路由电路中的功耗的系统和方法。 一个系统包括核心模块，适于接合多个核心模块的胶合逻辑域，以及电连接到胶合逻辑域的功率控制器。 每个胶合逻辑域包括实现为具有超出胶合逻辑模块的范围的金属迹线的软宏的胶合逻辑模块。 功率控制器基于核心模块和/或其他胶合逻辑域的控制信号和/或检测到的掉电状态来将电力与选定的胶合逻辑域分离。 功率控制器使用逻辑状态保持，逻辑状态钳位，有序或调度转换和/或其他功率转换系统和方法来促进功率转换。

公开(公告)号：US20140374873A1

公开(公告)日：2014-12-25

申请号：US14484904

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L23/538 ,  G06F17/50

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US09190358B2

公开(公告)日：2015-11-17

申请号：US14484904

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L29/00 ,  H01L21/82 ,  H01L23/538 ,  G06F17/50 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US08853815B1

公开(公告)日：2014-10-07

申请号：US13831360

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L29/00 ,  H01L21/82 ,  G06F17/50 ,  H01L29/06

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US09483600B2

公开(公告)日：2016-11-01

申请号：US14645336

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Mamta Bansal ,  Uday Doddannagari ,  Paras Gupta ,  Ramaprasath Vilangudipitchai ,  Parissa Najdesamii ,  Dorav Kumar ,  Nitin Partani

IPC: H01L25/00 ,  G06F17/50 ,  H01L27/02 ,  H04W72/04 ,  H01L23/528 ,  H01L27/092

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H04W72/0453 ,  Y02D70/00 ,  H01L2924/00

Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

Abstract translation: MOS器件包括多个标准单元，其被配置为减少路由拥塞，同时在MOS器件上提供区域节省。 标准细胞可以是共享与其他附近n型孔分离的n型井的单高度标准细胞。 单个高度标准单元的输入和输出信号引脚可以配置在最低可能的金属层（例如，M1）中，而单高度标准单元的次级电源引脚可以配置在较高的金属层（例如，M2 ）。 为次级电源引脚供电的互连可以沿着垂直轨道配置，并在不同的标准单元组之间共享，这可以减少在MOS器件中使用的垂直轨道的数量。 MOS器件中可用的水平路由轨迹的数量可能不受影响，因为主电源/接地网格已经使用的水平轨迹用于电源连接。

公开(公告)号：US09473113B1

公开(公告)日：2016-10-18

申请号：US14864101

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan ,  Lipeng Cao ,  Sai Pradeep Kochuri ,  Parissa Najdesamii

IPC: H03K3/02 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/35625

Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.

Abstract translation: 本文公开了一种用于通过具有保持特征的触发器来管理电力的集成电路（IC）。 在示例方面，IC包括恒定电源轨，可折叠电源轨，多个触发器和电源管理电路。 多个触发器的每个触发器包括耦合到可折叠电源轨的主部和耦合到恒功率轨的从部。 功率管理电路被配置为将时钟信号和保持信号组合成组合的控制信号，并将组合的控制信号提供给多个触发器的每个触发器。

公开(公告)号：US20140264715A1

公开(公告)日：2014-09-18

申请号：US13831360

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: G06F17/50 ,  H01L29/06

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.