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公开(公告)号：US09082498B2
公开(公告)日：2015-07-14
申请号：US13962702
申请日：2013-08-08
Applicant: QUALCOMM Incorporated
Inventor： Gregory Ameriada Uvieghara , Sei Seung Yoon
CPC classification number: G11C17/18 , G11C16/12 , G11C17/16 , H03K3/356113
Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.
Abstract translation: 公开了一种薄栅氧化物双模PMOS晶体管，其具有第一工作模式，其中双模PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路被配置为偏置开关n阱以防止对双模PMOS晶体管的电压损坏，而不使用天然晶体管。
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公开(公告)号：US08830779B1
公开(公告)日：2014-09-09
申请号：US13924916
申请日：2013-06-24
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Gregory Ameriada Uvieghara , Sei Seung Yoon , Balachander Ganesan , Anil Chowdary Kota
Abstract: A fuse-based memory includes a plurality of bit lines. Each bit lines couples to a corresponding plurality of fuses. The fuses couple to ground through corresponding access transistors. The memory is configured to precharge an accessed one of the bit lines and a reference one of the bit lines using a low voltage supply. In contrast, a resulting voltage difference between the accessed bit line and the reference bit line is sensed using a sense amplifier powered by a high voltage supply, wherein a high voltage supplied by the high power supply is greater than a low voltage supplied by the low voltage supply.
Abstract translation: 基于熔丝的存储器包括多个位线。 每个位线耦合到相应的多个保险丝。 保险丝通过相应的存取晶体管耦合到地。 存储器被配置为使用低电压电源对所访问的位线之一和位线中的参考一个进行预充电。 相比之下，使用由高压电源供电的读出放大器来感测访问的位线和参考位线之间产生的电压差，其中由高电源提供的高电压大于由低电压提供的低电压 电压供应
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公开(公告)号：US09318165B2
公开(公告)日：2016-04-19
申请号：US14218691
申请日：2014-03-18
Applicant: QUALCOMM Incorporated
Inventor： Chulmin Jung , Rui Li , Sei Seung Yoon , Gregory Ameriada Uvieghara
CPC classification number: G11C7/062 , G11C17/16 , G11C17/18 , H03F3/45183 , H03F3/45497 , H03F2203/45402 , H03F2203/45604 , H03F2203/45641 , H03F2203/45652
Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.
Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。
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公开(公告)号：US08787096B1
公开(公告)日：2014-07-22
申请号：US13742964
申请日：2013-01-16
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Gregory Ameriada Uvieghara , Sei Seung Yoon , Balachander Ganesan , Anil Chowdary Kota
CPC classification number: H03K17/223 , G11C7/00 , G11C7/12 , G11C8/08 , G11C13/0069 , G11C17/18 , H03K17/08104 , H03K17/6872 , H03K19/00315 , H03K2217/0018 , H03K2217/0063 , H03K2217/0072
Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。
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公开(公告)号：US20150043265A1
公开(公告)日：2015-02-12
申请号：US13962702
申请日：2013-08-08
Applicant: QUALCOMM Incorporated
Inventor： Gregory Ameriada Uvieghara , Sei Seung Yoon
CPC classification number: G11C17/18 , G11C16/12 , G11C17/16 , H03K3/356113
Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.
Abstract translation: 公开了一种薄栅氧化物双模PMOS晶体管，其具有第一工作模式，其中双模PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路被配置为偏置开关n阱以防止对双模PMOS晶体管的电压损坏，而不使用天然晶体管。
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Patent Agency Ranking
公开(公告)号：US08908464B2
公开(公告)日：2014-12-09
申请号：US13765559
申请日：2013-02-12
Applicant: QUALCOMM Incorporated
Inventor： Gregory Ameriada Uvieghara , Michael Batenburg , Esin Terzioglu , Yucong Tao
CPC classification number: G11C5/143 , G01R31/31719 , G01R31/3658 , G11C7/24
Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.
Abstract translation: 用于检测与集成电路上的次正常读取电压相关的电源攻击的系统和方法。 在启动集成电路的电源并且在从非易失性存储器（NVM）读取配置信息之前，首先读取与NVM相关联的测试单元。 测试单元与NVM共用公共电源，并且当在公共电源上施加次正常读取电压时，来自测试单元的输出读取值被配置为偏离测试单元中预编程的值。 因此，通过将输出读取值与预编程值进行比较，可以确定公共电源的电压是否是次正常，其中配置信息将在非正常读取电压下读取不正确。 如果电压低于正常值，则上电将中止。 否则，可以通过从NVM读取配置信息来上电。
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公开(公告)号：US20140226426A1
公开(公告)日：2014-08-14
申请号：US13765559
申请日：2013-02-12
Applicant: QUALCOMM INCORPORATED
Inventor： Gregory Ameriada Uvieghara , Michael Batenburg , Esin Terzioglu , Yucong Tao
IPC: G11C5/14
CPC classification number: G11C5/143 , G01R31/31719 , G01R31/3658 , G11C7/24
Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.
Abstract translation: 用于检测与集成电路上的次正常读取电压相关的电源攻击的系统和方法。 在启动集成电路的电源并且在从非易失性存储器（NVM）读取配置信息之前，首先读取与NVM相关的测试单元。 测试单元与NVM共用公共电源，并且当在公共电源上施加次正常读取电压时，来自测试单元的输出读取值被配置为偏离测试单元中预编程的值。 因此，通过将输出读取值与预编程值进行比较，可以确定公共电源的电压是否是次正常，其中配置信息将在非正常读取电压下读取不正确。 如果电压低于正常值，则上电将中止。 否则，可以通过从NVM读取配置信息来上电。
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公开(公告)号：US09252765B2
公开(公告)日：2016-02-02
申请号：US14472953
申请日：2014-08-29
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Gregory Ameriada Uvieghara , Sei Seung Yoon , Balachander Ganesan , Anil Chowdary Kota
IPC: G11C8/08 , H03K17/22 , G11C7/12 , G11C17/18 , H03K17/081 , H03K19/003 , G11C7/00 , H03K17/687 , G11C13/00
CPC classification number: H03K17/223 , G11C7/00 , G11C7/12 , G11C8/08 , G11C13/0069 , G11C17/18 , H03K17/08104 , H03K17/6872 , H03K19/00315 , H03K2217/0018 , H03K2217/0063 , H03K2217/0072
Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。
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公开(公告)号：US20150269978A1
公开(公告)日：2015-09-24
申请号：US14218691
申请日：2014-03-18
Applicant: QUALCOMM Incorporated
Inventor： Chulmin Jung , Rui Li , Sei Seung Yoon , Gregory Ameriada Uvieghara
CPC classification number: G11C7/062 , G11C17/16 , G11C17/18 , H03F3/45183 , H03F3/45497 , H03F2203/45402 , H03F2203/45604 , H03F2203/45641 , H03F2203/45652
Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.
Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。
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公开(公告)号：US20140369152A1
公开(公告)日：2014-12-18
申请号：US14472953
申请日：2014-08-29
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Gregory Ameriada Uvieghara , Sei Seung Yoon , Balachander Ganesan , Anil Chowdary Kota
IPC: H03K17/22 , H03K17/687 , G11C8/08
CPC classification number: H03K17/223 , G11C7/00 , G11C7/12 , G11C8/08 , G11C13/0069 , G11C17/18 , H03K17/08104 , H03K17/6872 , H03K19/00315 , H03K2217/0018 , H03K2217/0063 , H03K2217/0072
Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。
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