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公开(公告)号:US08910307B2
公开(公告)日:2014-12-09
申请号:US13715351
申请日:2012-12-14
Applicant: QUALCOMM Incorporated
Inventor: Sudeep Ravi Kottilingal , Gary Arthur Ciambella , Steven John Halter
IPC: G06F9/06 , H04N21/4385 , H04N21/426 , H04N21/443 , H04N21/835 , H04N21/4405 , G06F21/62 , H04N21/44 , H04L29/06
CPC classification number: G06F21/62 , G06F21/00 , H04L63/02 , H04N21/42623 , H04N21/42653 , H04N21/42692 , H04N21/43853 , H04N21/44004 , H04N21/4405 , H04N21/4431 , H04N21/4435 , H04N21/835
Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.
Abstract translation: 通常,本公开的方面涉及复制保护技术。 存储器中的区域可以被保护以在存储器中建立安全的存储器区域,该区域不被未经授权的客户端访问。 可以接收对存储在安全存储器区域中的视频内容进行解码的请求。 如果要解码的视频内容被存储在安全存储器区域中,则与硬件解码器相关联的第一MMU可以强制将视频内容解码为安全存储器区域中的一个或多个输出缓冲器的规则。 可以接收显示存储在安全存储器区域中的解码的视频内容的请求。 如果解码的视频内容存储在安全存储器区域中,则与硬件显示处理器相关联的第二MMU可以强制在硬件显示处理器和输出设备之间建立安全链路的规则。
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公开(公告)号:US11545114B2
公开(公告)日:2023-01-03
申请号:US17092165
申请日:2020-11-06
Applicant: QUALCOMM Incorporated
Inventor: Paul Christopher John Wiercienski , John Chi Kit Wong , Rahul Gulati , Gary Arthur Ciambella , Sreekanth Modaikkal
Abstract: The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.
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公开(公告)号:US20130305342A1
公开(公告)日:2013-11-14
申请号:US13715351
申请日:2012-12-14
Applicant: QUALCOMM INCORPORATED
Inventor: Sudeep Ravi Kottilingal , Gary Arthur Ciambella , Steven John Halter
IPC: G06F21/62
CPC classification number: G06F21/62 , G06F21/00 , H04L63/02 , H04N21/42623 , H04N21/42653 , H04N21/42692 , H04N21/43853 , H04N21/44004 , H04N21/4405 , H04N21/4431 , H04N21/4435 , H04N21/835
Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.
Abstract translation: 通常,本公开的方面涉及复制保护技术。 存储器中的区域可以被保护以在存储器中建立安全的存储器区域,该区域不被未经授权的客户端访问。 可以接收对存储在安全存储器区域中的视频内容进行解码的请求。 如果要解码的视频内容被存储在安全存储器区域中,则与硬件解码器相关联的第一MMU可以强制将视频内容解码为安全存储器区域中的一个或多个输出缓冲器的规则。 可以接收显示存储在安全存储器区域中的解码的视频内容的请求。 如果解码的视频内容存储在安全存储器区域中,则与硬件显示处理器相关联的第二MMU可以强制在硬件显示处理器和输出设备之间建立安全链路的规则。
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4.
公开(公告)号:US20240203376A1
公开(公告)日:2024-06-20
申请号:US18066034
申请日:2022-12-14
Applicant: QUALCOMM Incorporated
Inventor: Sreekanth Modaikkal , Kumar Saurabh , Gary Arthur Ciambella , Chun Wang , Anitha Madugiri Siddaraju
CPC classification number: G09G5/14 , G06T1/60 , G09G5/397 , G09G2340/10 , G09G2340/12
Abstract: Efficiently processing multiple non-overlapping layer images in display processing units is disclosed herein. In this regard, in some exemplary aspects, a display processing unit comprising a plurality of memory access pipeline circuits and a layer mixer circuit is provided. For each non-overlapping layer image of a plurality of non-overlapping layer images, a memory access pipeline circuit obtains image configuration data for the non-overlapping layer image, and fetches the non-overlapping layer image from an image data storage device based on the image configuration data. The memory access pipeline circuit then outputs each pixel of the non-overlapping layer image as part of an intermediate preblend image data stream based on the image configuration data. The layer mixer circuit blends the intermediate preblend image data stream and a background layer image data stream comprising a background layer image as a display data stream, and outputs the display data stream to a display device.
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