公开(公告)号：US20230352109A1

公开(公告)日：2023-11-02

申请号：US17909490

申请日：2021-01-26

申请人： Paul Scherrer Institut

发明人： Zhaochu Luo ,  Ales Hrabec ,  Laura J. Heyderman ,  Pietro Gambardella ,  Trong Phuong Dao

IPC分类号： G11C19/08 ,  H10N50/10 ,  G11C11/16 ,  H10N52/80 ,  H10N50/85 ,  H03K19/18

CPC分类号： G11C19/0841 ,  H10N50/10 ,  G11C11/161 ,  H10N52/80 ,  H10N50/85 ,  H03K19/18

摘要： A spin-based logic architecture provides nonvolatile data retention, near-zero leakage, and scalability. The architecture based on magnetic domain-walls take advantage of fast domain-wall motion, high density, non-volatility, and flexible design in order to process and store information. There is disclosed a concept to perform all-electric logic operations and cascading in domain-wall racetracks. The novel system exploits chiral coupling between neighboring magnetic domains induced by the interfacial Dzyaloshinskii-Moriya interaction to realize a domain-wall inverter. There are described reconfigurable NAND and NOR logic gates that perform operations with current-induced domain-wall motion. Several NAND gates are cascaded to build XOR and full adder gates, demonstrating electrical control of magnetic data and device interconnection in logic circuits. The novel system provides a viable platform for scalable all-electric magnetic logic and paves the way for memory-in-logic applications.