公开(公告)号：US4826785A

公开(公告)日：1989-05-02

申请号：US7065

申请日：1987-01-27

申请人： Paul J. McClure ,  Robert E. Jones, Jr.

发明人： Paul J. McClure ,  Robert E. Jones, Jr.

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S148/093

摘要： A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a fuse portion. A low energy laser having a Gaussian energy distribution focused on the absorptive layer produces heat in the absorptive layer. The heat is transferred to the underlying aluminum based interconnect. The concentration of energy made possible by the absorptive layer allows the low energy laser to blow the fuse thereby producing an electrical open in the interconnect without damaging surrounding silicon substrate and/or polysilicon structures below or nearby the metal fuse.

摘要翻译： 金属互连包括熔合部分，其在暴露于激光的辐射能时容易蒸发。 一层光学吸收材料形成在铝基金属互连的顶部上，并且它们通过光刻和蚀刻技术形成熔丝部分。 聚焦在吸收层上的具有高斯能量分布的低能激光在吸收层中产生热量。 热转移到下面的铝基互连。 通过吸收层使能量的浓度允许低能量激光器熔断熔丝，从而在互连中产生电开路，而不会损坏金属保险丝下方或附近的周围的硅衬底和/或多晶硅结构。

公开(公告)号：US4935801A

公开(公告)日：1990-06-19

申请号：US304361

申请日：1989-01-30

申请人： Paul J. McClure ,  Robert E. Jones, Jr.

发明人： Paul J. McClure ,  Robert E. Jones, Jr.

IPC分类号： H01L21/768 ,  H01L23/525

CPC分类号： H01L23/5258 ,  H01L21/76888 ,  H01L2924/0002 ,  Y10S257/915

摘要： A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a fuse portion. A low energy laser having a Gaussian energy distribuution focused on the absorptive layer produces heat in the absorptive layer. The heat is transferred to the underlying aluminum based interconnect. The concentration of energy made possible by the absorptive layer allows the low energy laser to blow the fuse thereby producing an electrical open in the interconnect without damaging surrounding silicon substrate and/or polysilicon structures below or nearby the metal fuse.

摘要翻译： 金属互连包括熔合部分，其在暴露于激光的辐射能时容易蒸发。 一层光学吸收材料形成在铝基金属互连的顶部上，并且它们通过光刻和蚀刻技术形成熔丝部分。 具有聚焦在吸收层上的高斯能量分布的低能激光在吸收层中产生热量。 热转移到下面的铝基互连。 通过吸收层使能量的浓度允许低能量激光器熔断熔丝，从而在互连中产生电开路，而不会损坏金属保险丝下方或附近的周围的硅衬底和/或多晶硅结构。

公开(公告)号：US5716875A

公开(公告)日：1998-02-10

申请号：US609697

申请日：1996-03-01

申请人： Robert E. Jones, Jr. ,  Peir-Yung Chu ,  Peter Zurcher ,  Ajay Jain

发明人： Robert E. Jones, Jr. ,  Peir-Yung Chu ,  Peter Zurcher ,  Ajay Jain

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/00

CPC分类号： H01L27/11502 ,  H01L21/8221 ,  H01L21/8238 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/11507 ,  H01L28/55

摘要： A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

摘要翻译： 通过形成CMOS晶体管（37a，37b，40,42），可以在单个衬底（10）上形成CMOS晶体管和铁电电容器的方法以提高的产量开始。 进行使用4-5％氢和余量氮的氢退火以减少晶体管（37a，37b，40,42）的栅介质/衬底界面处的悬挂原子键。 然后在晶体管和晶片衬底（10）的背面上沉积氮化硅层（48），以便基本上将氢退火的影响封装到CMOS晶体管（37a，37b，40,42）。 铁电电容器层（54,58,60,62,64）形成在氮化物层（48）上，其中铁电电容器层（54,58,60,62,64）在纯O2中进行氧退火。 氮化物层（48）防止晶体管氢退火通过包含氢而损坏铁电材料。

公开(公告)号：US5439840A

公开(公告)日：1995-08-08

申请号：US100793

申请日：1993-08-02

申请人： Robert E. Jones, Jr. ,  Papu D. Maniar

发明人： Robert E. Jones, Jr. ,  Papu D. Maniar

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L29/92 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10808 ,  H01L28/55

摘要： A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

摘要翻译： 具有金属氧化物电介质层的电容器形成有电连接到下面的电路元件的上电极层。 电容器可用于形成用于DRAM和NVRAM单元的存储电容器。 在形成诸如晶体管的源极/漏极区域的底层电路元件之后，在电路元件上形成金属氧化物电容器。 通过电容器形成开口并延伸到电路元件。 形成绝缘间隔物，并且形成将电路元件与金属氧化物电容器的上电极层电连接的导电部件。 公开了包括DRAM和NVRAM单元的器件及其形成方法。

公开(公告)号：US06531731B2

公开(公告)日：2003-03-11

申请号：US09881332

申请日：2001-06-15

申请人： Robert E. Jones, Jr. ,  Bruce E. White, Jr.

发明人： Robert E. Jones, Jr. ,  Bruce E. White, Jr.

IPC分类号： H01L2906

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C2216/06 ,  H01L21/28273 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11521 ,  H01L29/7883 ,  Y10S438/981

摘要： Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

公开(公告)号：US5949624A

公开(公告)日：1999-09-07

申请号：US943779

申请日：1997-10-03

申请人： Randall G. Simmons ,  Robert E. Jones, Jr.

发明人： Randall G. Simmons ,  Robert E. Jones, Jr.

IPC分类号： G11B5/00 ,  G11B5/23 ,  G11B5/245 ,  G11B5/31 ,  G11B5/39

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/23 ,  G11B5/3183 ,  G11B5/3906 ,  G11B5/3967 ,  G11B2005/0008 ,  G11B2005/0013 ,  G11B2005/3996 ,  G11B5/245

摘要： An inductive-write magnetoresistive-read horizontal head for magnetic recording having two polarization conductors. The two polarization conductors are used to simultaneously activate a MR sensor and to disable the write head during the read back process to eliminate the secondary read back signal from the inductive-write head. During the read process, the current through a first conductor biases the MR stripe while current through the second conductor generates an applied field to switch the magnetization of the Permalloy (NiFe) in the write head pole and reduce the permeability. The head incorporates write-wide read-narrow head attributes and has the reliability advantages associated with yoke or recessed MR or GMR structures. The magnetoresistive stripe may be disposed directly in the gap of the heads or it may be recessed.

摘要翻译： 用于具有两个偏振导体的磁记录的感应写入磁阻读取水平头。 两个偏振导体用于同时激活MR传感器并且在回读过程期间禁用写入头以消除来自电感写入头的二次回读信号。 在读取过程中，通过第一导体的电流偏置MR条，同时通过第二导体的电流产生施加的场，以切换写磁头极中的坡莫合金（NiFe）的磁化并降低磁导率。 头部包含写入宽度窄的头部属性，并具有与磁轭或嵌入式MR或GMR结构相关的可靠性优势。 磁阻条可以直接设置在磁头的间隙中，也可以是凹陷的。

公开(公告)号：US5405796A

公开(公告)日：1995-04-11

申请号：US182470

申请日：1994-01-18

申请人： Robert E. Jones, Jr.

发明人： Robert E. Jones, Jr.

IPC分类号： H01G4/33 ,  H01G4/40 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC分类号： H01L28/55 ,  H01L27/10808

摘要： A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

摘要翻译： 一种用于存储单元（10）的电容器。 形成在衬底（10）上的晶体管。 晶体管具有第一电流电极（16）和第二电流电极（18）。 电流电极（16和18）被沟道区分开。 栅极电极（26）形成在沟道区域的上方，并通过栅介质层（24）与沟道区物理分离。 插塞区域（32）被形成为覆盖并电连接到第一电流电极（16）。 形成在晶体管上方并由高介电常数介电层（36）形成的环形高介电常数介电区（33）。 第一电容器电极经由导电区域（38“）形成，并且第二电容器电极经由导电区域（38'）形成。 可以根据环状高电容率介电区域（33）的各种特性，将存储单元（10）形成为非易失性存储单元或DRAM单元。

公开(公告)号：US5313089A

公开(公告)日：1994-05-17

申请号：US887942

申请日：1992-05-26

申请人： Robert E. Jones, Jr.

发明人： Robert E. Jones, Jr.

IPC分类号： H01G4/33 ,  H01G4/40 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/68

CPC分类号： H01L28/55 ,  H01L27/10808

摘要： A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

摘要翻译： 一种用于存储单元（10）的电容器。 形成在衬底（10）上的晶体管。 晶体管具有第一电流电极（16）和第二电流电极（18）。 电流电极（16和18）被沟道区分开。 栅极电极（26）形成在沟道区域的上方，并通过栅介质层（24）与沟道区物理分离。 插塞区域（32）被形成为覆盖并电连接到第一电流电极（16）。 形成在晶体管上方并由高介电常数介电层（36）形成的环形高介电常数介电区（33）。 第一电容器电极经由导电区域（38“）形成，并且第二电容器电极经由导电区域（38'）形成。 可以根据环状高电容率介电区域（33）的各种特性，将存储单元（10）形成为非易失性存储单元或DRAM单元。

公开(公告)号：US06790727B2

公开(公告)日：2004-09-14

申请号：US10348267

申请日：2003-01-21

申请人： Robert E. Jones, Jr. ,  Bruce E. White, Jr.

发明人： Robert E. Jones, Jr. ,  Bruce E. White, Jr.

IPC分类号： H01L21336

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C2216/06 ,  H01L21/28273 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11521 ,  H01L29/7883 ,  Y10S438/981

摘要： Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.

摘要翻译： 非易失性存储器（NVM）和动态纳米晶体存储器（DNM）都集成在半导体衬底上。 具有嵌入式纳米晶体或离散存储元件的控制栅极和控制电介质形成在不同厚度的隧道电介质上以形成两个存储器。 源极和漏极区域形成在与隧道电介质相邻的半导体衬底内。 通过添加最小的加工步骤，可以使用各种方法形成薄的隧道氧化物和厚的隧道氧化物。

公开(公告)号：US06344413B1

公开(公告)日：2002-02-05

申请号：US09022756

申请日：1998-02-12

申请人： Peter Zurcher ,  Robert E. Jones, Jr. ,  Papu D. Maniar ,  Peir Chu

发明人： Peter Zurcher ,  Robert E. Jones, Jr. ,  Papu D. Maniar ,  Peir Chu

IPC分类号： H01L2170

CPC分类号： H01L21/3212 ,  H01L27/1057 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65

摘要： Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.

摘要翻译： 用于形成具有电容器的半导体器件的方法，其中电容器嵌入形成在半导体衬底中的空腔中，并且部分高密度存储器。 一个实施例首先在空腔中形成底部电极，然后用牺牲层填充空腔，以允许电容器电极中的至少一个的化学机械抛光（CMP）。 在去除底部电极的部分和牺牲层的部分之后，形成介电层。 然后在电介质层上形成顶部电极。 这样形成的电介质层将底部电极与顶部电极隔离，防止短路和漏电流。 在一个实施例中，为多个底部电极形成单个顶部电极层，从而降低了存储器电路的复杂性。