Abstract:
Aligning memory access operations to a geometry of a storage device, including: receiving, by a storage array controller, information describing the layout of memory in the storage device; determining, by the storage array controller, a write size in dependence upon the layout of memory in the storage device; and sending, by the storage array controller, a write request addressed to a location within the memory unit in dependence upon the layout of memory in the storage device.
Abstract:
Exposing a geometry of a storage device, including: sending, by the storage device, information describing the layout of memory in the storage device; receiving, by the storage device, a write request, the write request associated with an amount of data sized in dependence upon the layout of memory in the storage device; and writing, by the storage device, the data to a memory unit, the data written to a location within the memory unit in dependence upon the layout of memory in the storage device.
Abstract:
A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.
Abstract:
Multiple allocation units are selected from a set of solid state storage devices for storage of data. An erasure code and intra-device recovery data associated with the data are generated. The intra-device recovery data is written in each of the plurality of allocation units of the set of solid-state storage devices. The erasure code is written in a subset of the plurality of allocation units.
Abstract:
One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
Abstract:
A read request with a high priority indication is received. A determination as to whether an in progress flash programming operation would delay processing the read request for a threshold amount of time is made. In response to determining that the in progress flash programming operation delays processing the read request for the threshold amount of time, the in progress flash programming operation is interrupted.
Abstract:
A method includes, responsive to receiving a modified first reservation command from a storage controller, identifying, by a storage drive, a first range of storage based on a first range identifier of the modified reservation command. The method also includes granting, by the storage drive, a reservation for access to the storage drive on behalf of a first host controller by associating the reservation for the first range with a second range of storage.
Abstract:
A system with storage memory and a processing device has a logical deletion to physical erasure time bound. The system dereferences data, responsive to a direction to delete the data. The system monitors physical blocks in storage memory for live data and the dereferenced data. The system cooperates garbage collection with monitoring the physical blocks, so that at least a physical block having the dereferenced data is garbage collected and erased within a logical deletion to physical erasure time bound.
Abstract:
Buffering data to be written to an array of non-volatile storage devices, including: receiving a request to write data to the array of non-volatile storage devices; sending, to a non-volatile random access memory (‘NVRAM’) device, an instruction to write the data to dynamic random access memory (‘DRAM’) in the NVRAM device, the DRAM configured to receive power from a primary power source, the DRAM further configured to receive power from a backup power source in response to the primary power source failing; and writing the data to the DRAM in the NVRAM device.