公开(公告)号：US09716079B2

公开(公告)日：2017-07-25

申请号：US15214465

申请日：2016-07-20

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chia-Wei Chang ,  Kuo-Ting Lin

IPC: H01L23/02 ,  H01L21/50 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2225/06506 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00

Abstract: A multi-chip package having no substrate is presented. The multi-chip package includes a chip stacked assembly, a first redistribution layer, a plurality of wire bonds, a plurality of metal pillars, an encapsulation, a second redistribution layer, and a plurality of vertical interposers. The first redistribution layer and the second redistribution layer are used in place of a substrate to reduce the thickness of the multi-chip package. In this way, a package-on-package device formed using the multi-chip package has a reduced thickness.

公开(公告)号：US20170033084A1

公开(公告)日：2017-02-02

申请号：US15214465

申请日：2016-07-20

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chia-Wei Chang ,  Kuo-Ting Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/78 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2225/06506 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00

Abstract: A multi-chip package having no substrate is presented. The multi-chip package includes a chip stacked assembly, a first redistribution layer, a plurality of wire bonds, a plurality of metal pillars, an encapsulation, a second redistribution layer, and a plurality of vertical interposers. The first redistribution layer and the second redistribution layer are used in place of a substrate to reduce the thickness of the multi-chip package. In this way, a package-on-package device formed using the multi-chip package has a reduced thickness.

Abstract translation: 提出了一种没有衬底的多芯片封装。 多芯片封装包括芯片堆叠组件，第一再分布层，多个引线键合，多个金属柱，封装，第二再分配层和多个垂直插入件。 使用第一再分布层和第二再分布层代替衬底以减小多芯片封装的厚度。 以这种方式，使用多芯片封装形成的封装封装器件具有减小的厚度。

公开(公告)号：US10304716B1

公开(公告)日：2019-05-28

申请号：US15847936

申请日：2017-12-20

Applicant: Powertech Technology Inc.

Inventor： Hsing-Te Chung ,  Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Nan-Chun Lin

IPC: H01L21/683 ,  H01L23/498 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68309 ,  H01L2221/68368 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

公开(公告)号：US09659911B1

公开(公告)日：2017-05-23

申请号：US15264606

申请日：2016-09-14

Applicant: Powertech Technology Inc.

Inventor： Chia-Wei Chang ,  Li-Chih Fang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer (RDL), at least one first die, a plurality of conductive terminals and solder balls, a first encapsulant, a plurality of second dies, and a second encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first die and the conductive terminals are electrically connected to the RDL and are located on the first surface of the RDL. The first encapsulant encapsulates the first die and the conductive terminals. The first encapsulant exposes part of the conductive terminals. The solder balls are electrically connected to the conductive terminals and are located over the conductive terminals exposed by the first encapsulant. The second dies are electrically connected to the RDL and are located on the second surface of the RDL. The second encapsulant encapsulates the second dies.

公开(公告)号：US20170309597A1

公开(公告)日：2017-10-26

申请号：US15491982

申请日：2017-04-20

Applicant: Powertech Technology Inc.

Inventor： Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Li-Chih Fang ,  Chia-Jen Chou

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

公开(公告)号：US09673178B2

公开(公告)日：2017-06-06

申请号：US14970558

申请日：2015-12-16

Applicant: Powertech Technology Inc.

Inventor： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20170110439A1

公开(公告)日：2017-04-20

申请号：US14970558

申请日：2015-12-16

Applicant: Powertech Technology Inc.

Inventor： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US20190189494A1

公开(公告)日：2019-06-20

申请号：US15847936

申请日：2017-12-20

Applicant: Powertech Technology Inc.

Inventor： Hsing-Te Chung ,  Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Nan-Chun Lin

IPC: H01L21/683 ,  H01L23/498 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68309 ,  H01L2221/68368 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

公开(公告)号：US20180145015A1

公开(公告)日：2018-05-24

申请号：US15876210

申请日：2018-01-22

Applicant: Powertech Technology Inc.

Inventor： Kuo-Ting Lin ,  Chia-Wei Chang

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/1058 ,  H01L2924/1816 ,  H01L2924/18162

Abstract: A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.

公开(公告)号：US10121736B2

公开(公告)日：2018-11-06

申请号：US15876210

申请日：2018-01-22

Applicant: Powertech Technology Inc.

Inventor： Kuo-Ting Lin ,  Chia-Wei Chang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538

Abstract: A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.