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公开(公告)号：US11791281B2
公开(公告)日：2023-10-17
申请号：US16824425
申请日：2020-03-19
发明人： You-Lung Yen , Pao-Hung Chou , Chun-Hsien Yu
IPC分类号： H01L23/00 , H01L23/31 , H01L23/14 , H01L23/498 , H01L21/48 , H01L21/56 , H01L21/683
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/565 , H01L21/6835 , H01L23/145 , H01L23/3128 , H01L23/49838 , H01L24/16 , H01L2224/16227 , H01L2924/3511 , H01L2924/35121
摘要： A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
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公开(公告)号：US11749619B2
公开(公告)日：2023-09-05
申请号：US16824425
申请日：2020-03-19
发明人： You-Lung Yen , Pao-Hung Chou , Chun-Hsien Yu
IPC分类号： H01L23/00 , H01L23/31 , H01L23/14 , H01L23/498 , H01L21/48 , H01L21/56 , H01L21/683
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/565 , H01L21/6835 , H01L23/145 , H01L23/3128 , H01L23/49838 , H01L24/16 , H01L2224/16227 , H01L2924/3511 , H01L2924/35121
摘要： A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
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公开(公告)号：US20220328613A1
公开(公告)日：2022-10-13
申请号：US17686744
申请日：2022-03-04
发明人： Pao-Hung Chou , Chun-Hsien Yu , Shih-Ping Hsu
IPC分类号： H01L49/02 , H01L23/498 , H01L23/552 , H01L23/64
摘要： An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.
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公开(公告)号：US10347575B2
公开(公告)日：2019-07-09
申请号：US15227350
申请日：2016-08-03
发明人： Chun-Hsien Yu , Shih-Ping Hsu , Pao-Hung Chou , Chi-Feng Peng
IPC分类号： H05K3/40 , H05K3/46 , H01L21/02 , H01L23/28 , H01L23/498 , H01L21/683 , H01L21/48
摘要： This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first dielectric material layer have an opening; a first conductive unit including a first part in the opening of the first dielectric material layer and a second part on the first dielectric material layer; and a second dielectric material layer covering the first conductive unit and the first dielectric material layer; wherein a height of the first conductive unit is larger than a thickness of the first dielectric material layer; wherein a cross-section of the second part is larger than that of the first part in the first conductive unit.
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5.发明申请公开(公告)号：US20200312756A1
公开(公告)日：2020-10-01
申请号：US16832084
申请日：2020-03-27
发明人： Pao-Hung Chou , Chun-Hsien Yu , Shih-Ping Hsu
IPC分类号： H01L23/498 , H01L21/48
摘要： A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.
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公开(公告)号：US20190074196A1
公开(公告)日：2019-03-07
申请号：US15823831
申请日：2017-11-28
发明人： Chun-Hsien Yu , Hsien-Ming Tsai
CPC分类号： H01L21/56 , H01L21/4825 , H01L21/4846 , H01L23/3121 , H01L23/3128 , H01L23/36 , H01L23/49811 , H01L2224/48091 , H01L2224/73265 , H01L2924/01029 , H01L2924/181 , H05K1/0209 , H05K2201/066
摘要： The present disclosure provides an electronic package, including a package substrate and an electronic component formed on the package substrate. The substrate includes an insulating portion, a wiring portion embedded in the insulating portion, and a metal board disposed on the insulating portion and in contact with the wiring portion. The metal board is provided with a plurality of electrical contacts and a heat dissipating portion. The metal board can maintain a predefined heat dissipation area via the heat dissipating portion, and be connected to a circuit board via the electrical contacts.
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公开(公告)号：US09852977B2
公开(公告)日：2017-12-26
申请号：US15351838
申请日：2016-11-15
发明人： Chun-Hsien Yu , Pao-Hung Chou
IPC分类号： H05K1/00 , H01L23/498 , H05K1/11 , H05K1/03
CPC分类号： H01L23/49894 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H05K1/0271 , H05K1/036 , H05K1/0393 , H05K1/115 , H05K3/28 , H05K2201/0376
摘要： This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed on the rigid dielectric material layer, and a first flexible dielectric material layer formed on the first wiring layer.
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公开(公告)号：US09711445B2
公开(公告)日：2017-07-18
申请号：US15054861
申请日：2016-02-26
发明人： Chun-Hsien Yu , Shih-Ping Hsu
IPC分类号： H01L23/02 , H01L23/498
CPC分类号： H01L23/4985 , H01L23/49822 , H01L23/49827 , H01L23/49861
摘要： This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first wiring layer having a first metal wire and a first dielectric material layer surrounding the first metal wire; a conductive pillar layer formed on the first wiring layer and including a first metal pillar connected to the first metal wire and a molding compound layer surrounding the first metal pillar; a flexible material layer formed on the conductive pillar layer and including a first opening formed on the first metal pillar and exposing the first metal pillar; and a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the first metal pillar through the first opening, a second metal pillar formed on the second metal wire, and a protective layer surrounding the second metal wire and the second metal pillar.
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公开(公告)号：US12094922B2
公开(公告)日：2024-09-17
申请号：US17686744
申请日：2022-03-04
发明人： Pao-Hung Chou , Chun-Hsien Yu , Shih-Ping Hsu
IPC分类号： H01L23/64 , H01L23/498 , H01L23/552 , H01L49/02
CPC分类号： H01L28/10 , H01L23/49822 , H01L23/49838 , H01L23/552 , H01L23/645
摘要： An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.
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公开(公告)号：US20210098351A1
公开(公告)日：2021-04-01
申请号：US17020984
申请日：2020-09-15
发明人： Pao-Hung Chou , Chun-Hsien Yu , Shih-Ping Hsu
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H05K1/03 , H05K3/46
摘要： A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.
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