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208 条记录 (耗时 0.028 秒)

    Orientation independent oxidation of nitrided silicon
    1.
    发明授权
    Orientation independent oxidation of nitrided silicon 失效
    氮化硅的取向独立氧化

    公开(公告)号：US06727142B1

    公开(公告)日：2004-04-27

    申请号：US10284508

    申请日：2002-10-29

    申请人： Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Helmut H. Tews

    发明人： Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Helmut H. Tews

    IPC分类号： H01L2126

    CPC分类号： H01L21/02332 ,  H01L21/02247 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/32105

    摘要： Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

    摘要翻译： 形成垂直MOS晶体管或在硅晶片中制造另一三维集成电路结构暴露具有至少两个不同晶体取向的平面。 不同晶面上生长的氧化物固有地在不同的生长速率下，因为不同平面中原子间的间距是不同的。 在含氮环境中加热硅以形成氮化物薄层，然后通过薄氮化层生长氧化物，将氧化物厚度的差异减小到小于1％。

    Method of fabricating a buried collar
    3.
    发明授权
    Method of fabricating a buried collar 失效
    埋地衣领的制作方法

    公开(公告)号：US06838334B1

    公开(公告)日：2005-01-04

    申请号：US10604562

    申请日：2003-07-30

    申请人： Oleg Gluschenkov ,  Chung-Yung Sung ,  Helmut H. Tews

    发明人： Oleg Gluschenkov ,  Chung-Yung Sung ,  Helmut H. Tews

    IPC分类号： H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/31662 ,  H01L27/10864 ,  H01L27/1087

    摘要： A method of forming a buried collar on the sidewall of a trench in a semiconductor substrate including: (a) providing the trench in the semiconductor substrate, the trench having a first dielectric layer formed on a sidewall in a upper region of the trench and a conductive material filling a lower region of the trench, the conductive material covering a lower portion of the first dielectric layer; (b) removing the first dielectric layer not covered by the conductive material; (c) forming a second dielectric layer on the exposed sidewall of the upper region and on a top surface of the conductive material; (d) removing an uppermost portion of the second dielectric layer from the sidewall in the upper region; (e) forming a third dielectric layer on the exposed sidewall of the upper region; and (f) increasing the thickness of the second dielectric layer to form the buried collar.

    Shallow trench isolation for device including deep trench capacitors
    6.
    发明授权
    Shallow trench isolation for device including deep trench capacitors 失效
    用于包括深沟槽电容器的器件的浅沟槽隔离

    公开(公告)号：US08679938B2

    公开(公告)日：2014-03-25

    申请号：US13366576

    申请日：2012-02-06

    申请人： Sunfei Fang ,  Oleg Gluschenkov ,  Byeong Y. Kim ,  Rishikesh Krishnan ,  Daewon Yang

    发明人： Sunfei Fang ,  Oleg Gluschenkov ,  Byeong Y. Kim ,  Rishikesh Krishnan ,  Daewon Yang

    IPC分类号： H01L21/20

    CPC分类号： H01L27/10861 ,  H01L21/76224 ,  H01L29/66181 ,  H01L29/945

    摘要： A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.

    摘要翻译： 在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽 ，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

    Application of cluster beam implantation for fabricating threshold voltage adjusted FETs
    8.
    发明授权
    Application of cluster beam implantation for fabricating threshold voltage adjusted FETs 有权
    应用聚束束注入制造阈值电压调节FET

    公开(公告)号：US08288222B2

    公开(公告)日：2012-10-16

    申请号：US12582139

    申请日：2009-10-20

    申请人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

    发明人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857

    摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

    摘要翻译： 提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。 所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从 聚束束植入步骤后的结构。

    STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR
    9.
    发明申请
    STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR 有权
    高K金属栅极半导体晶体管的结构

    公开(公告)号：US20120098067A1

    公开(公告)日：2012-04-26

    申请号：US12908024

    申请日：2010-10-20

    申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

    发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

    IPC分类号： H01L27/092 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

    摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

    摘要翻译： 提供半导体结构。 该结构包括直接在应变硅层的顶部形成的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。

    Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
    10.
    发明授权
    Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof 有权
    具有混合体厚度的FET的集成电路芯片及其制造方法

    公开(公告)号：US07968944B2

    公开(公告)日：2011-06-28

    申请号：US12541641

    申请日：2009-08-14

    申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

    发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

    IPC分类号： H01L27/12 ,  H01L29/00

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

    摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

    摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。