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    Power-connection/car-mounting device
    1.
    发明授权
    Power-connection/car-mounting device 失效
    电源连接/车载装置

    公开(公告)号：US4767337A

    公开(公告)日：1988-08-30

    申请号：US875583

    申请日：1986-06-18

    Applicant: Nobuhiko Kawasaki ,  Kouichi Ikeda ,  Shinichi Kimura

    Inventor： Nobuhiko Kawasaki ,  Kouichi Ikeda ,  Shinichi Kimura

    IPC: A47J27/21 ,  H01R33/975 ,  H01R13/639

    CPC classification number: H01R33/975 ,  A47J27/21166 ,  Y10S403/01 ,  Y10T403/604

    Abstract: A device and system for connecting a car-mounted apparatus comprising a fixing plate installed to part of a car body for supporting the car-mounted apparatus, a female part formed in either the car-mounted apparatus or the fixing plate, and a male part extending from either the car-mounted apparatus or the fixing plate that can be freely engaged with and disengaged from the female part. The invention also relates to a device for supplying power to a car-mounted apparatus by electrically connecting a connector on the car-body and a connector on the car-mounted apparatus, where either of these connectors is installed so that it can freely move and integrally vibrate with the other connector when in an engaged condition.

    Abstract translation: 一种用于连接车载装置的装置和系统，包括安装到用于支撑车载装置的车体的一部分的固定板，形成在车载装置或固定板中的阴部件和阳部件 从可以自由接合和从母部分脱离的车载装置或固定板延伸。 本发明还涉及一种用于通过电连接车体上的连接器和车载装置上的连接器来向车载装置供电的装置，其中这些连接器中的任一个安装成可以自由移动， 当处于接合状态时与另一个连接器一体地振动。

    Method for manufacturing semiconductor device
    3.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06479306B1

    公开(公告)日：2002-11-12

    申请号：US09716165

    申请日：2000-11-17

    Applicant: Kouichi Ikeda ,  Takeshi Ikeda

    Inventor： Kouichi Ikeda ,  Takeshi Ikeda

    IPC: G01R3126

    CPC classification number: H01L22/20 ,  G11C29/006 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/00

    Abstract: A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality of semiconductor chips of different kinds (processor chip and memory chip) are formed on a semiconductor wafer, and a go/no-go test is conducted on all the chips. The semiconductor wafer is cut and divided into pieces that each consist of a good processor chip and a good memory chip, and they are mounted on a substrate to form a semiconductor module.

    Abstract translation: 一种用于制造可高密度安装的半导体器件的半导体器件和方法，其包括简化的工艺，但能够降低缺陷率。 在半导体晶片上形成多个不同种类的半导体芯片（处理器芯片和存储器芯片），并且对所有芯片进行去/不进行测试。 将半导体晶片切割并分成各自由良好的处理器芯片和良好的存储器芯片组成的片，并将它们安装在基板上以形成半导体模块。

    Transfer system
    4.
    发明授权
    Transfer system 失效
    转移系统

    公开(公告)号：US06986417B2

    公开(公告)日：2006-01-17

    申请号：US10661507

    申请日：2003-09-15

    Applicant: Yoshihiro Nishizawa ,  Masami Mitsuhashi ,  Keiichi Kubota ,  Kouichi Ikeda ,  Hideo Murakami

    Inventor： Yoshihiro Nishizawa ,  Masami Mitsuhashi ,  Keiichi Kubota ,  Kouichi Ikeda ,  Hideo Murakami

    IPC: B65G47/10

    CPC classification number: B23P19/001 ,  B23P21/004 ,  B23P2700/50 ,  B23Q7/1447 ,  B62D65/18 ,  B65G37/02

    Abstract: A transfer system includes transfer lines (L) each of which forms a closed loop and has transfer-in stations (S1 and S3) and transfer-out stations (S2 and S4) for assembling parts to a work, while circulating the work along the transfer line (L); and a work and part transfer passage (51) for transferring the work and the parts. Transfer-in stations (S1 and S3) and the transfer-out stations (S2 and S4) are disposed at each of the longitudinal ends of each of the transfer lines (L). Sub-transfer-passages (521 and 522) branching out rightward and leftward from the work and part transfer passage (51), are disposed along longitudinal sides of the transfer lines (L). With this layout, a plurality of the transfer lines (L) can be disposed in a required minimum space, while securing a smooth supply and discharge of the works and parts with respect to the plurality of the transfer lines L.

    Abstract translation: 传送系统包括传输线（L），每条传输线形成一个闭环，并具有传送站（S 1和S 3）和传送站（S 在工件沿着传送线（L）循环的同时，将零件组装到工件上;以及（2） 以及用于传送作业和部件的工件和部件传送通道（51）。 转移站（S＆lt; 1＆gt;和S＆gt; 3＆gt;）和转出站（S＆lt; 2＆gt;和S＆gt; 4＆lt; >）设置在每个传送线（L）的每个纵向端。 沿着工件和部件传送通道（51）向右和向左分支的副传送通道（52 1和52 2）沿着转印件的纵向侧布置 线（L）。 通过这种布局，可以在所需的最小空间内设置多条传输线（L），同时确保工件和部件相对于多条输送线路L的平稳供应和排出。

    IMAGE PICKUP APPARATUS AND METHOD, LENS UNIT AND COMPUTER EXECUTABLE PROGRAM
    6.
    发明申请
    IMAGE PICKUP APPARATUS AND METHOD, LENS UNIT AND COMPUTER EXECUTABLE PROGRAM 审中-公开
    图像拾取装置和方法，透镜单元和计算机可执行程序

    公开(公告)号：US20080309772A1

    公开(公告)日：2008-12-18

    申请号：US12123854

    申请日：2008-05-20

    Applicant: Kouichi Ikeda

    Inventor： Kouichi Ikeda

    IPC: H04N5/228 ,  G03B17/00

    CPC classification number: G03B5/00 ,  H04N5/23248

    Abstract: A digital still camera includes a lens system having a variable focal length. An image pickup unit is disposed on an optical axis of the lens system, for forming an image frame. Yaw and pitch rate sensors detect a camera shake to output shake information. A shake correction mechanism, associated with an anti-vibration lens, compensates for the camera shake by shifting perpendicularly to the optical axis according to the shake information. A memory stores an LUT of correlation information between the focal length and a shift amount of the shake correction mechanism to compensate for an image shake of the image frame created due to a change in the focal length. In case of lack of detected camera shake with the yaw and pitch rate sensors, the shake correction mechanism is controlled with a shift amount associated with the focal length according to the LUT.

    Abstract translation: 数码相机包括具有可变焦距的透镜系统。 图像拾取单元设置在透镜系统的光轴上，用于形成图像帧。 偏航速率传感器检测相机抖动以输出抖动信息。 与防振透镜相关联的抖动校正机构根据抖动信息通过垂直于光轴移动来补偿相机抖动。 存储器存储焦距和抖动校正机构的偏移量之间的相关信息的LUT，以补偿由于焦距变化而产生的图像帧的图像抖动。 在偏航和俯仰速率传感器缺乏检测到的相机抖动的情况下，根据LUT对与焦距相关联的偏移量来控制抖动校正机构。

    Device and method for testing semiconductor device
    7.
    发明授权
    Device and method for testing semiconductor device 有权
    半导体器件测试装置及方法

    公开(公告)号：US08917103B2

    公开(公告)日：2014-12-23

    申请号：US13198879

    申请日：2011-08-05

    Applicant: Koichi Morino ,  Kouichi Ikeda

    Inventor： Koichi Morino ,  Kouichi Ikeda

    IPC: G01R31/10 ,  G01R31/02 ,  H01L35/00 ,  G01R31/28

    CPC classification number: G01R31/2875

    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection function activating temperature range.

    Abstract translation: 用于测试半导体器件的测试方法包括加热半导体器件直到半导体器件的温度达到预定温度; 在半导体器件的温度达到预定温度之后，在第二步骤中进行除了过热保护功能的测试之外的其他功能测试; 允许半导体器件自身产生热量，使得半导体器件的过热保护功能被激活，当半导体器件的过热保护功能被激活时，检测包含在半导体器件中的所需二极管的第一二极管正向电压，并且计算 基于所检测的半导体器件中包含的所需二极管的第二二极管正向电压的半导体器件的第一计算温度; 以及确定所计算的半导体器件的第一计算温度是否存在于过热保护功能激活温度范围内。

    Transfer system
    8.
    发明授权
    Transfer system 失效
    转移系统

    公开(公告)号：US06626282B1

    公开(公告)日：2003-09-30

    申请号：US09807988

    申请日：2001-08-10

    Applicant: Yoshihiro Nishizawa ,  Masami Mitsuhashi ,  Keiichi Kubota ,  Kouichi Ikeda ,  Hideo Murakami

    Inventor： Yoshihiro Nishizawa ,  Masami Mitsuhashi ,  Keiichi Kubota ,  Kouichi Ikeda ,  Hideo Murakami

    IPC: B65G2900

    CPC classification number: B23Q7/1447 ,  B23P19/001 ,  B23P21/004 ,  B23P2700/50 ,  B62D65/18 ,  B65G37/02

    Abstract: A transfer line (L) is formed by a first conveyer (C1) and a second conveyer (C2) which are disposed in parallel to each other for transferring a pallet, a first traverser (T1) for transporting the pallet (P) from a terminal end of the first conveyer (C1) to a start end of the second conveyer (C2), and a second traverser (T2) for transporting the pallet (P) from a terminal end of the second conveyer (C2) to a start end of the first conveyer (C1). The first and second conveyers (C1 and C2) are operable to drive main drive rollers (22) provided at start ends of the conveyers by bringing the rollers into abutment against side surfaces of rearmost pallets (P) in the advancing direction, thereby urging and collectively driving a plurality of pallets (P) which are connected together forwardly of the rearmost pallets (P) in a state in contact with the rearmost pallets. This enables the length of the transfer line (L) to be changed as desired without modification of a drive device for the pallet (P).

    Abstract translation: 传送线（L）由彼此平行设置以传送托盘的第一输送机（C1）和第二输送机（C2）形成，用于将托盘（P）运送到第一横动器（T1） 第一输送机（C1）的末端到第二输送机（C2）的起始端，以及用于将托盘（P）从第二输送机（C2）的末端输送到起始端的第二横动器（T2） 的第一输送机（C1）。 第一和第二输送机（C1和C2）可操作以通过使滚子在前进方向上抵靠最后面托盘（P）的侧表面来驱动设置在输送机起始端的主驱动辊（22），由此推动和 集体地驱动在与最后面托盘接触的状态下将最后托盘（P）向前连接的多个托盘（P）。 这样可以根据需要改变输送线（L）的长度，而不改变托盘（P）的驱动装置。

    Memory module
    9.
    发明授权
    Memory module 有权
    内存模块

    公开(公告)号：US06208546B1

    公开(公告)日：2001-03-27

    申请号：US09284614

    申请日：1999-06-24

    Applicant: Kouichi Ikeda

    Inventor： Kouichi Ikeda

    IPC: G11C502

    CPC classification number: H01L23/5386 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

    Abstract: An object of the present invention is to provide a memory module capable of being mounted easily on various memory boards or mother boards, having a large memory capacity, and requiring a small mounting area. The memory module 10 includes four memory bare chips 1 scribed from a semiconductor wafer and mounted on a module board 2 by the COB technology. The module board 2 is formed with a row of pads 4 near the center portion in the longitudinal direction of the module board 2. Two memory bare chips 1 are disposed on the module board 2 at opposite sides of the pads 4. Each memory bare chip 1 is formed with pads 3 along the center line and the pads 3 are connected to the pads 4 on the module board 2 by the use of bonding wires 5. The bonding wires 5 and the memory bare chips 1 are covered with a plastic resin 6. Also, the module board 2 is formed with external connection terminals 8 on the outer side edges for connection to a memory board or a mother board by the LCC technology.

    Abstract translation: 本发明的目的是提供一种能够容易地安装在具有大存储容量并且需要小的安装区域的各种存储器板或母板上的存储器模块。 存储器模块10包括从半导体晶片刻划并通过COB技术安装在模块板2上的四个存储器裸芯片1。 模块板2在模块板2的纵向方向上的中心部分附近形成有一排垫4.两个存储器裸芯片1在焊盘4的相对侧设置在模块板2上。每个存储器裸芯片 1沿着中心线形成有焊盘3，并且焊盘3通过使用接合线5连接到模块板2上的焊盘4.接合线5和存储器裸芯片1被塑料树脂6覆盖 此外，模块板2在外侧边缘上形成有外部连接端子8，用于通过LCC技术连接到存储器板或母板。

    Device and method for testing semiconductor device
    10.
    发明授权
    Device and method for testing semiconductor device 有权

    公开(公告)号：US08860445B2

    公开(公告)日：2014-10-14

    申请号：US13198879

    申请日：2011-08-05

    Applicant: Koichi Morino ,  Kouichi Ikeda

    Inventor： Koichi Morino ,  Kouichi Ikeda

    IPC: G01R31/10 ,  G01R31/02 ,  H01L35/00 ,  G01R31/28

    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection function activating temperature range.

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